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參數資料
| 型號： | AD9432BST-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 431K |
| 代理商： | AD9432BST-80 |
REV. B
AD9432
–9–
APPLICATION NOTES
Theory of Operation
The AD9432 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to frequencies near
Nyquist. DNL transitional errors are calibrated at final test to a
typical accuracy of 0.25 LSB or less.
USING THE AD9432
ENCODE Input
Any high speed A/D converter is extremely sensitive to the qual-
ity of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9432, and the
user is advised to give commensurate thought to the clock
source. The ENCODE input supports either differential or
single-ended and is fully TTL/CMOS compatible.
Note that the ENCODE inputs cannot be driven directly
from PECL level signals (V
IHD
is 3.5 V max). PECL level
signals can easily be accommodated by ac coupling as shown
in Figure 23. Good performance is obtained using an MC10EL16
in the circuit to drive the encode inputs.
GND
510
510
0.1 F
0.1 F
PECL
GATE
ENCODE
ENCODE
AD9432
Figure 23. AC Coupling to ENCODE Inputs
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and
ENCODE
in single-ended and differential mode are shown in Figure 24.
ENCODE Inputs
Differential Signal Amplitude (V
ID
) . . . . . . . . . . . 500 mV min,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mV nom
High Differential Input Voltage (V
IHD
) . . . . . . . . . . 3.5 V max
Low Differential Input Voltage (V
ILD
) . . . . . . . . . . . . . 0 V min
Common-Mode Input (V
ICM
) . . . . . . . 1.25 V min, 1.6 V nom
High Single-Ended Voltage (V
IHS
) . . . . . 2 V min to 3.5 V max
Low Single-Ended Voltage (V
ILS
) . . . . . 0 V min to 0.8 V max
ENCODE
ENCODE
ENCODE
0.1 F
V
ID
V
IHD
V
ICM
V
ILD
V
IHS
V
ILS
Figure 24. Differential and Single-Ended Input Levels
Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.
Digital Outputs
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOS-
compatible for lower power consumption.
Analog Input
The analog input to the AD9432 is a differential buffer. The input
buffer is self-biased by an on-chip resistor divider that sets the
dc common-mode voltage to a nominal 3 V (see Equivalent
Circuits section). Rated performance is achieved by driving the
input differentially. Minimum input offset voltage is obtained when
driving from a source with a low differential source impedance
such as a transformer in ac applications. Capacitive coupling at the
inputs will increase the input offset voltage by as much as
±
25 mV.
Driving the ADC single-endedly will degrade performance.
For best dynamic performance, impedances at AIN and
AIN
should match.
Special care was taken in the design of the analog input section
of the AD9432 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 2.0 V p-p.
Each analog input will be 1 V p-p when driven differentially.
2.5
3.5
4.0
2.0
3.0
AIN
AIN
Figure 25. Full-Scale Analog Input Range
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9432 (VREFOUT). In normal operation the internal refer-
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1
μ
F
decoupling capacitor at VREFIN.
The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in perfor-
mance occurs when the reference is adjusted
±
5%. The full-scale
range of the ADC tracks reference voltage changes linearly.
Timing
The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (see Figure 1).
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9432;
these transients can detract from the converter’s dynamic
performance.
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