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參數資料
| 型號： | AD9433 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| 中文描述： | 12位，105 MSPS/125 MSPS的中頻采樣的A / D轉換器 |
| 文件頁數： | 13/24頁 |
| 文件大小： | 1001K |
| 代理商： | AD9433 |
REV. 0
AD9433
–13–
APPLICATION NOTES
Theory of Operation
The AD9433 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this
converter
provides flat dynamic performance up to and beyond the Nyquist
limit.
DNL transitional errors are calibrated at final test to a
typical accuracy of 0.25 LSB or less.
USING THE AD9433
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD9433, and the
user is
advised to give commensurate thought to the clock source.
The AD9433 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling edge
of
ENCODE
if driven differentially), and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern, and is not
reduced by the internal stabilization circuit. This circuit is
always on, and cannot be disabled by the user.
The ENCODE and
ENCODE
inputs are internally biased to
3.75 V (nominal), and support either differential or single-
ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained using
an MC10EL16 in the circuit to directly drive the encode
inputs, as illustrated in Figure 7.
FREQUENCY
–
MHz
–
120
0
11.52
d
–
110
–
100
–
90
–
80
–
70
–
60
–
50
–
40
–
30
–
20
–
10
0
23.04
34.56
46.08
TPC 32. FFT: f
S
= 92.16 MSPS, f
IN
= 70.3 MHz, WCDMA @
70.0 MHz, SFDR Enabled
ENCODE
ENCODE
PECL
GATE
510
510
AD9433
Figure 7. Using PECL to Drive the
ENCODE
Inputs
Often, the cleanest clock source is a crystal oscillator producing
a pure, single-ended sine wave. In this configuration, or with
any roughly symmetrical, single-ended clock source, the signal
can be ac-coupled to the ENCODE input. To minimize jitter,
the signal amplitude should be maximized within the input
range described in Table I below. The 12 k
resistors to
ground at each of the inputs, in parallel with the internal bias
resistors, set the common-mode voltage to approximately 2.5 V,
allowing the maximum swing at the input. The
ENCODE
input
should be bypassed with a capacitor to ground to reduce noise.
This ensures that the internal bias voltage is centered on the
encode signal. For best dynamic performance, impedances at
ENCODE and
ENCODE
should match.
ENCODE
ENCODE
AD9433
50
25
12k
12k
0.1 F
0.1 F
50
SINE
SOURCE
Figure 8. Single-Ended Sine Source Encode Circuit
FREQUENCY
–
MHz
–
120
0
9.6
d
–
110
–
100
–
90
–
80
–
70
–
60
–
50
–
40
–
30
–
20
–
10
0
19.2
28.8
38.4
TPC 31. FFT: f
S
= 76.8 MSPS, f
IN
= 59.6 MHz, 2 WCDMA
Carriers, Differential AIN, SFDR Enabled
相關PDF資料 |
PDF描述 |
|---|---|
| AD9433BSQ-105 | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9444BSVZ-80 | 14-Bit, 80 MSPS, A/D Converter |
| AD9444 | 14-Bit, 80 MSPS, A/D Converter |
| AD9445-IF-PCB | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| AD9445BSVZ-105 | 14-Bit, 105/125 MSPS, IF Sampling ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9433/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9433BSQ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 105 MSPS ADC - Bulk |
| AD9433BSQ-125 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 125Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 125 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9433BSQZ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP |
| AD9433BSQZ-125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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