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參數(shù)資料
| 型號(hào)： | AD9433 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| 中文描述： | 12位，105 MSPS/125 MSPS的中頻采樣的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 1001K |
| 代理商： | AD9433 |
REV. 0
AD9433
–6–
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a fullscale response. Peak differen-
tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak to peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
ENOB
SNR
dB
Amplitude
Input Amplitude
MEASURED
=
–1 76
+
Full-Scale
.
20
6 02
log
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE
pulse should be left in logic
“
1
”
state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing impli-
cations of changing t
ENCH
in text. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
Z
Full Scale
FullScale
rms
=
10
0 001
.
2
log
Gain
Gain error is the difference between the measured and ideal
full-scale input voltage range of the ADC.
Harmonic Distortion
The ratio of the rms signal amplitude fundamental frequency to
the rms signal amplitude of a single harmonic component (second,
third, etc.), reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best fit straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The maximum encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for Any Range within the ADC)
V
=
Z
0.001
10
FS
–
SNR
–
Signal
10
NOISE
dBm
dBc
dBFS
×
×
Where
Z
is the input impedance,
FS
is the full scale of the device
for the frequency in question,
SNR
is the value for the particular
input level, and
SIGNAL
is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (i.e.,
degrades as signal level is lowered), or dBFS (always related back
to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone (f
1
, f
2
) to the rms
value of the worst third order intermodulation product; reported
in dBc. Products are located at 2f
1
–
f
2
and 2f
2
–
f
1
.
Two-Tone SFDR
The ratio of the rms value of either input tone (f
1
, f
2
) to the rms
value of the peak spurious component. The peak spurious com-
ponent may or may not be an IMD product. May be reported in
dBc (i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9433BSQ-105 | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9444BSVZ-80 | 14-Bit, 80 MSPS, A/D Converter |
| AD9444 | 14-Bit, 80 MSPS, A/D Converter |
| AD9445-IF-PCB | 14-Bit, 105/125 MSPS, IF Sampling ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9433/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9433BSQ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 105 MSPS ADC - Bulk |
| AD9433BSQ-125 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 125Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 125 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9433BSQZ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP |
| AD9433BSQZ-125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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