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參數資料
| 型號： | AD9433BSQ-105 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52 |
| 封裝： | POWER, PLASTIC, LQFP-52 |
| 文件頁數： | 16/24頁 |
| 文件大小： | 1001K |
| 代理商： | AD9433BSQ-105 |
REV. 0
AD9433
–16–
Table VI. Power Supply Connections for the AD9433 Evaluation Board
Connector
Pin
Designator
External Supply Required
Approximate Current Level
P42
P1, P3
P2
P4
P1, P3
P2
P4
GND
–
5 V (Optional U10 Supply)
V
DL
GND
V
O
V
CC
Ground
–
5 V
+3 V
Ground
+3 V
+5 V
30 mA
144 mA
P43
10 mA
325 mA Without U10
355 mA With U10
Evaluation Board
The AD9433 evaluation board offers designers an easy way to
evaluate device performance. The user must supply an analog
input signal, encode clock reference, and power supplies. The
digital outputs of the AD9433 are latched on the evaluation
board, and are available with a data ready signal at a 40-pin
edge connector. Please refer to the evaluation board schematic,
layout, and bill of materials that follow.
Power Connections
Power to the board is supplied via two detachable, four-pin
power strips (P42 and P43). These eight pins should be driven
as outlined in Table VI. Please note that the
–
5 V supply is
optional, and only required if the user adds differential op amp
U10 to the board.
Jumper Options
The table below describes the jumper options on the AD9433
Evaluation board.
Table VII. AD9433 Evaluation Board Jumper Options
Jumper
Designation
Connection
Configuration
SFDR
5 V
SFDR Enhancement
Circuit Enabled
SFDR Enhancement
Circuit Disabled
Offset Binary Output
Data Format
Two
’
s Complement
Output Data Storage
Output Register (U7
–
U8)
Clock is Buffered
Output Register (U7
–
U8)
Clock is Inverted
Data Ready Signal is
Buffered
Data Ready Signal is
Inverted
GND
DFS
5 V
GND
LATCH
E10 to E6
E10 to E5
DATA READY
E7 to E8
E7 to E9
Encode Signal and Distribution
The encode input signal should drive SMB connector P38,
which has an on-board 50
termination. This signal is ac-coupled,
and may be either a low jitter pulse or a sine wave reference,
with up to 4 V p-p amplitude. U2 (MC10EP16) converts this
single-ended input signal to a differential PECL signal to drive
the AD9433. U1 (DS90LV048A) also converts the signal at P38
to a CMOS level signal to drive the clock inputs of the two out-
put data registers U7
–
U8, (74LVT574WM), the reconstruction
DAC U3 (AD9772AAST), and the output data connector.
Analog Input
The analog input signal is ac-coupled to the evaluation board by
SMB connector P39. Transformers T1 and T2 (ADT1-1WT)
convert this signal to a differential signal to drive AIN and
AIN
of the AD9433. These RF transformers are specified as 1:1, but
their turns ratio is actually 6:7. T1 is rotated 180
°
and mounted
on the board such that its secondary and primary are reversed,
making its ratio 7:6. The second transformer in series now form
a combined 1:1 turns ration for the analog signal, and provide a
50
termination for connector J1 via 25
resistors R3 and R4.
Resistor R3, normally omitted, can be used to terminate P39 if
the transformers are removed for single ended drive. In this
configuration, the user will need to short the input signal from
Pin 3 of T1 to Pin 6 of T2, and remove resistor R4. Resistor R3
should remain in place to match the impedance of AIN and
AIN.
Using the AD8350
An optional driver circuit for the analog input, based on the
AD8350 differential amplifier, is included in the layout of the
AD9433 evaluation board. This portion of the evaluation circuit
is not populated when the board is manufactured, but can be
easily added by the user. Removing resistors R29 and R30 will
disconnect the normal analog input signal path, and populating
R17 and R31 will connect the AD8350 output network.
DAC Reconstruction Circuit
The data available at output connector U2 is also reconstructed
by DAC U3, the AD772A. This 14-bit, high-speed
digital-to-
analog converter is included as a tool in setting up and debugging the
evaluation board. It should not be used to measure the performance
of the AD9433, as its performance will not accurately reflect the
performance of the ADC. As configured on the AD9433 evaluation
board, the AD9772A divides the input clock frequency by a factor
of two, and ignores every other sample from the AD9433. The
AD9772 internally interpolates the missing samples so that the
DAC output will reflect the input of the AD9433 only when the
analog input frequency is less than or equal to 1/4 the ADC
encode rate. The AD9772 requires offset binary format so the
DFS jumper should be connected to 5 V. The DAC
’
s output,
available at J1, will drive 50
. The user may move the jumper
wire between E43 and E42 to connect E43 to E44, thus activating
the SLEEP function of the DAC.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9433BSQ-125 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 125Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 125 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9433BSQZ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP |
| AD9433BSQZ-125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9433BSVZ-105 | 功能描述:IC ADC 12BIT 105MSPS 52TQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9433BSVZ-125 | 功能描述:IC ADC 12BIT 125MSPS 52-TQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
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