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參數資料
| 型號： | AD9444BSVZ-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, A/D Converter |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | LEAD FREE, PLASTIC, MS-026-AED, TQFP-100 |
| 文件頁數： | 13/40頁 |
| 文件大小： | 1291K |
| 代理商： | AD9444BSVZ-80 |
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AD9444
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
Mnemonic
Description
1, 8 to 9, 16 to 18,
24 to 27, 34 to 35,
38, 41 to 42, 87,
89 to 95, 98
2 to 4, 7,
43 to 46, 49 to 52,
55 to 60, 65
5
OUTPUT
MODE
Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS
mode, and OUTPUT MODE =
1 (AVDD1) for LVDS outputs.
6
DFS
Data Format Select Pin.
CMOS control pin that de-
termines the format of the
output data. DFS = high
(AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
10
SENSE
Reference Mode Selection.
Connect to AGND for internal
1 V reference, and connect to
AVDD2 for external reference.
11
VREF
1.0 V Reference I/O—
Function Dependent on
SENSE. Decouple to ground
with 0.1 μF and 10 μF
capacitors.
12, 15, 20, 23,
32, 86, 88, 96 to
97, 99, Exposed
Heat Sink
connected to AGND.
13
REFT
Differential Reference Out-
put. Decoupled to ground
with 0.1 μF capacitor and to
REFB (Pin 14) with 0.1 μF and
10 μF capacitors.
14
REFB
Differential Reference Out-
put. Decoupled to ground
with a 0.1 μF capacitor and to
REFT (Pin 13) with 0.1 μF and
10 μF capacitors.
19, 28 to 31,
39 to 40
21
VIN+
Analog Input—True.
22
VIN
Analog Input—Complement.
Rev. 0 | Page 13 of 40
AVDD1
3.3 V (±5%) Analog Supply.
DNC
Do Not Connect. These
pins should float.
CMOS Compatible Output
AGND
Analog Ground. The exposed
heat sink on the bottom of
the package must be
AVDD2
5.0 V Analog Supply (±5%).
Pin No.
33
Mnemonic
C1
Description
Internal Bypass Node.
Connect a 0.1 μF capacitor
from this pin to AGND.
Clock Input—True.
Clock Input—Complement.
3.3 V Digital Output
Supply (2.5V to 3.6 V).
Digital Ground.
36
37
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
63
CLK+
CLK
DRVDD
DRGND
DCO
Data Clock Output—
Complement (CMOS Levels).
Data Clock Output—
True.
D0 Output Bit (LSB)
(CMOS Levels).
D1 Output Bit.
D2 Output Bit.
D3 Output Bit.
D4 Output Bit.
D5 Output Bit.
D6 Output Bit.
D7 Output Bit.
D8 Output Bit.
D9 Output Bit.
D10 Output Bit.
D11 Output Bit.
D12 Output Bit.
D13 Output Bit.
Out-of-Range Output.
Clock Duty Cycle Stabilizer
(DCS) Control Pin, CMOS-
Compatible. DCS = low
(AGND) to enable DCS
(recommended). DCS =
high (AVDD1) to disable DCS.
64
DCO+
66
D0 (LSB)
68
69
70
71
72
73
76
77
78
79
80
81
84
85
100
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13 (MSB)
OR
DCS MODE
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