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參數資料
| 型號： | AD9445BSVZ-105 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | LEAD FREE, PLASTIC, MS-026-AED, TQFP-100 |
| 文件頁數： | 26/40頁 |
| 文件大小： | 965K |
| 代理商： | AD9445BSVZ-105 |
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AD9445
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to-
digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9445, and the user is
advised to give careful thought to the clock source.
Rev. 0 | Page 26 of 40
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9445 contains a clock duty
cycle stabilizer (DCS) that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. Noise and distortion performance are nearly flat for a
30% to 70% duty cycle with the DCS enabled. The DCS circuit
locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than
30 MHz nominally. The loop is associated with a time constant
that should be considered in applications where the clock rate
can change dynamically, requiring a wait time of 1.5 μs to 5 μs
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time that
the loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle
stabilizer, and logic high (AVDD1 = 3.3 V) disables the
controller.
The AD9445 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
when using a high jitter clock source. (See the AN-501
Application Note
,
Performance.) For optimum performance, the AD9445 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
the CLK+ and CLK pins via a transformer or capacitors.
Figure 64 shows one preferred method for clocking the
AD9445. The clock source (low jitter) is converted from single-
ended to differential using an RF transformer. The back-to-back
Schottky diodes across the secondary of the transformer limit
clock excursions into the AD9445 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9445
and limits the noise presented to the sample clock inputs.
If a low jitter clock is available, it may help to band-pass filter
the clock reference before driving the ADC clock inputs.
Another option is to ac couple a differential ECL/PECL signal
to the encode input pins, as shown in Figure 65
.
0
0.1
μ
F
AD9445
CLK+
CLK–
HSMS2812
DIODES
CLOCK
SOURCE
ADT1–1WT
Figure 64. Crystal Clock Oscillator, Differential Encode
0
0.1
μ
F
AD9445
ENCODE
ENCODE
0.1
μ
F
VT
VT
ECL/
PECL
Figure 65. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (
f
INPUT
) and rms amplitude due only to aperture jitter
(
t
J
) can be calculated using the following equation:
SNR
= 20 log[2
π
f
INPUT
×
t
J
]
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which includes the clock
input, analog input signal, and ADC aperture jitter
specification. IF undersampling applications are particularly
sensitive to jitter, see Figure 66.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9445. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or another
method), it should be synchronized by the original clock during
the last step.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9445BSVZ-125 | 功能描述:IC ADC 14BIT 125MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數:12 采樣率（每秒）:1.8M 數據接口:并聯 轉換器數目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數目和類型:2 個單端，單極 |
| AD9445-IF-LVDS | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC |
| AD9445-IF-LVDS/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 14-Bit, 105/125 MAPA, IF Sampling ADC 制造商:Analog Devices 功能描述:EVAL KIT FOR 14BIT, 105/125 MSPS, IF SAMPLING ADC - Bulk |
| AD9445IF-LVDS/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9445IF 制造商:Analog Devices 功能描述:14-BIT 125 MSPS ADC IF EVAL BD - Bulk |
| AD9445-IF-LVDSPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
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