欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號: AD9445BSVZ-105
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 105/125 MSPS, IF Sampling ADC
中文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: LEAD FREE, PLASTIC, MS-026-AED, TQFP-100
文件頁數(shù): 6/40頁
文件大?。?/td> 965K
代理商: AD9445BSVZ-105
AD9445
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R
LVDS_BIAS
= 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)
1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)
V
OD
Differential Output Voltage
2
V
OS
Output Offset Voltage
CLOCK INPUTS (CLK+, CLK)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
1
Output voltage levels measured with 5 pF load on each output.
2
LVDS R
TERM
= 100 Ω.
Rev. 0 | Page 6 of 40
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
2.0
10
2
3.25
247
1.125
0.2
1.3
1.5
1.1
1.4
2
AD9445BSVZ-125
Min
Typ
2.0
10
2
3.25
247
1.125
0.2
1.3
1.5
1.1
1.4
2
Unit
V
V
μA
μA
pF
V
V
mV
V
V
V
pF
Max
0.8
200
+10
0.2
545
1.375
1.6
1.7
Max
0.8
200
+10
0.2
545
1.375
1.6
1.7
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High
1
(t
CLKH
)
CLK Pulse Width Low
1
(t
CLKL
)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (t
PD
)
2
(Dx, DCO+)
Output Propagation Delay—LVDS (t
PD
)
3
(Dx+), (t
CPD
)
3
(DCO+)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter, t
J
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
105
9.5
3.8
3.8
3.35
2.1
3.6
13
60
AD9445BSVZ-125
Min
Typ
125
8.0
3.2
3.2
3.35
2.3
3.6
13
60
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
fsec
rms
Max
10
4.8
Max
10
4.8
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS R
TERM
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
相關PDF資料
PDF描述
AD9445BSVZ-125 14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445 14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445-BB-LVDS 14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445-BB-PCB 14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445-IF-LVDS 14-Bit, 105/125 MSPS, IF Sampling ADC
相關代理商/技術參數(shù)
參數(shù)描述
AD9445BSVZ-125 功能描述:IC ADC 14BIT 125MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率(每秒):1.8M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散(最大):1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP(7x7) 包裝:管件 輸入數(shù)目和類型:2 個單端,單極
AD9445-IF-LVDS 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445-IF-LVDS/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 14-Bit, 105/125 MAPA, IF Sampling ADC 制造商:Analog Devices 功能描述:EVAL KIT FOR 14BIT, 105/125 MSPS, IF SAMPLING ADC - Bulk
AD9445IF-LVDS/PCBZ 制造商:Analog Devices 功能描述:Evaluation Board For AD9445IF 制造商:Analog Devices 功能描述:14-BIT 125 MSPS ADC IF EVAL BD - Bulk
AD9445-IF-LVDSPCB 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit
主站蜘蛛池模板: 繁昌县| 南昌市| 资兴市| 贡山| 富平县| 彩票| 涞源县| 安化县| 华宁县| 芦山县| 兴宁市| 卓资县| 赤水市| 鸡东县| 玛曲县| 南川市| 临江市| 宁南县| 长乐市| 夹江县| 永和县| 清水河县| 峨眉山市| 宜川县| 绍兴县| 会昌县| 湖北省| 疏勒县| 阳泉市| 克拉玛依市| 九台市| 柳河县| 夏河县| 荣昌县| 广丰县| 乌鲁木齐市| 噶尔县| 宜黄县| 平罗县| 神农架林区| 诸城市|