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參數(shù)資料
| 型號： | AD9446BSVZ-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 80/100 MSPS ADC |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | EXPOSEDPAD, LEAD FREE, PLASTIC, MS-026-AED, TQFP-44 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 952K |
| 代理商： | AD9446BSVZ-80 |
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AD9446
Rev. 0 | Page 26 of 36
0
0.1
μ
F
R
T
AD9446
VIN+
VIN–
R
S
R
S
ADT1–1WT
ANALOG
INPUT
SIGNAL
Figure 58. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to-
digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9446, and the user is
advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9446 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal ~50% duty cycle. Noise and distortion per-
formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9446 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of per-
formance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
high jitter clock source. (See the AN-501 Application Note
,
optimum performance, the AD9446 must be clocked differentially. The sample clock inputs are internally biased to ~1.5 V, and the
input signal is usually ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. Figure 59 shows one preferred
method for clocking the AD9446. The clock source (low jitter)
is converted from single-ended to differential using an RF trans-
former. The back-to-back Schottky diodes across the secondary
of the transformer limit clock excursions into the AD9446 to
approximately 0.8 V p-p differential. This helps prevent the large
voltage swings of the clock from feeding through to other portions
of the AD9446 and limits the noise presented to the sample
clock inputs.
If a low jitter clock is available, it may help to band-pass filter
the clock reference before driving the ADC clock inputs. Another
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in Figure 60.
0
0.1
μ
F
AD9446
CLK+
CLK–
HSMS2812
DIODES
CRYSTAL
SINE
SOURCE
ADT1–1WT
Figure 59. Crystal Clock Oscillator, Differential Encode
0
0.1
μ
F
AD9446
ENCODE
ENCODE
0.1
μ
F
VT
VT
ECL/
PECL
Figure 60. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (
f
INPUT
) and rms amplitude due only to aperture jitter
(
t
J
) can be calculated using the following equation:
SNR
= 20 log[2
π
f
INPUT
×
t
J
]
In the equation, the rms aperture jitter represents the root-mean-
square of all jitter sources, which includes the clock input, analog
input signal, and ADC aperture jitter specification. IF under-
sampling applications are particularly sensitive to jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9446.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.
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