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參數(shù)資料
型號: AD9446BSVZ-80
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 80/100 MSPS ADC
中文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: EXPOSEDPAD, LEAD FREE, PLASTIC, MS-026-AED, TQFP-44
文件頁數(shù): 28/36頁
文件大小: 952K
代理商: AD9446BSVZ-80
AD9446
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9446 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Rev. 0 | Page 28 of 36
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS-
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9446 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9446 outputs are LVDS compatible, and
the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
Table 10. Digital Output Coding
VIN+ VIN
Input Span = 3.2 V p-p (V)
65,536
+1.600
32,768
0
32,767
0.0000488
0
1.60
Code
VIN+ VIN
Input Span = 2 V p-p (V)
+1.000
0
0.000122
1.00
Digital Output
Offset Binary (D15D0)
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Digital Output
Twos Complement (D15D0)
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
相關(guān)PDF資料
PDF描述
AD9446 16-Bit, 80/100 MSPS ADC
AD9446-100LVDS 16-Bit, 80/100 MSPS ADC
AD9446-100PCB 16-Bit, 80/100 MSPS ADC
AD9446-80LVDS 16-Bit, 80/100 MSPS ADC
AD9446-80PCB 16-Bit, 80/100 MSPS ADC
相關(guān)代理商/技術(shù)參數(shù)
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