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參數資料
| 型號： | AD9501 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | 數字可編程延時發生器 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 180K |
| 代理商： | AD9501 |
AD9501
REV. A
–4–
AD9501 PIN DE SCRIPT IONS
Pin No.
Name
Function
1
2
+V
S
LAT CH
Positive voltage supply; nominally +5 V.
T T L/CMOS register control line. Logic HIGH latches input data D
0
–D
7
. Register is
transparent for logic LOW.
T T L/CMOS-compatible input. Rising edge triggers the internal ramp generator, and begins
the delay cycle.
T T L/CMOS-compatible input. Logic HIGH resets the ramp voltage and OUT PUT .
Output voltage of the internal digital-to-analog converter.
Optional external capacitor connected to +V
S
; used with R
SET
and 8.5 pF internal capacitor
to determine full-scale delay range (t
DFS
).
External resistor to ground, used to determine full-scale delay range (t
DFS
).
Normally connected to GROUND. Can be used to adjust minimum propagation delay (t
PD
);
see T heory of Operation text.
Circuit ground return.
T T L-compatible delayed output pulse.
Positive voltage supply; nominally +5 V.
T T L/CMOS-compatible inputs, used to set the programmed delay of the AD9501 delayed
output. D
0
is LSB and D
7
is MSB.
Circuit ground return.
3
T RIGGER
4
5
6
RESET
DAC OUT PUT
C
EX T
7
8
R
SET
OFFSET ADJUST
9
10
11
12-19
GROUND
OUT PUT
+V
S
D
0
–D
7
20
GROUND
AD9501 Equivalent Circuits
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9501 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
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