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參數(shù)資料
| 型號： | AD9501 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | 數(shù)字可編程延時發(fā)生器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 180K |
| 代理商： | AD9501 |
AD9501
REV. A
–8–
For most applications, OUT PUT can be tied to RESET . T his
causes the output pulse to be narrow (equal to the Reset
Propagation Delay t
RD
). Alternatively, an external pulse can be
applied to RESET . T o assure a valid output pulse, however, the
delay between T RIGGER and RESET should be equal to or
greater than the total delay of t
PD
+ t
D
illustrated in the internal
timing diagram Figure 1.
As shown in that figure, the capacitor voltage discharges very
rapidly and includes a small amount of overshoot and ringing.
Rated timing delay will not be realized unless subsequent trigger
events are delayed until after the linear ramp settles to its reset
voltage value.
T he values for the various delay increments in the specification
table are based on a Full-Scale Delay Range of 100 ns with
OUT PUT tied to RESET (self-resetting operation).
When Full-Scale Delay Range is set for intervals shorter than
100 ns, the rate of change of the linear ramp is increased. T his
faster rate means the Maximum T rigger Rate shown in the
specification table is increased because the Ramp Generator
Delay and, consequently, Minimum Propagation Delay t
PD
become smaller.
Linear Ramp Settling T ime t
LRS
also becomes shorter as Full-
Scale Delay Range is decreased. Minimum Delays for various
Full-Scale Delay Range values are shown in Figure 2.
APPLIC AT IONS
T he AD9501 is useful in a wide variety of precision timing
applications because of its ability to delay T T L/ CMOS pulse
edges by increments as small as 10 ps.
Figure 4. AD9501 Typical Circuit Configuration
In Figure 4, the AD9501 typical circuit configuration, the
delayed output is tied back to the RESET input. T his will pro-
duce a narrow output pulse whose leading edge is delayed by an
amount proportional to the 8-bit digital word stored in the on-
board latches. For the configuration shown, the output pulse
width will be equal to the Reset Propagation Delay (t
RD
). If
wider pulses are required, a delay can be inserted between
OUT PUT and RESET . If preferred, an external pulse can be
used as a reset input to control the timing of the falling edge
(and consequently, the width) of the delayed output.
Multiple Signal Path Deskewing
High speed electronic systems with parallel signal paths require
that close delay matching be maintained. If delay mismatch
(time skew) occurs, errors can occur during data transfer. For
these situations, the matching of delays is generally accom-
plished by carefully matching lead lengths.
Figure 5. Multiple Signal Path Deskewing
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