- 您現在的位置：買賣IC網 > PDF目錄373963 > AD9501JQ (ANALOG DEVICES INC) Digitally Programmable Delay Generator PDF資料下載
參數資料
| 型號： | AD9501JQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 180K |
| 代理商： | AD9501JQ |
AD9501
REV. A
–5–
Figure 1, the AD9501 Internal T iming diagram, illustrates in
detail how the delay is determined. Minimum Delay (t
PD
) is the
sum of T rigger Circuit delay, Ramp Generator delay, and
Comparator delay.
T he T rigger Circuit delay and Comparator delay are fixed;
Ramp Generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Maximum Delay is the sum of Minimum Delay (t
PD
) and Full-
Scale Program Delay (t
DFS
).
Ramp Generator delay is the time required for the ramp to slew
from its reset voltage to the most positive DAC reference
voltage (00
H
). T he difference in these two voltages is nominally
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
T HE ORY OF OPE RAT ION
T he AD9501 is a digitally programmable delay device. Its
function is to provide a precise incremental delay between input
and output, proportional to an 8-bit digital word applied to its
delay control port. Incremental delay resolution is 10 ps at the
minimum full-scale range of 2.5 ns. Digital delay data inputs,
latch, trigger and reset are all T T L/CMOS compatible. Output
is T T L-compatible.
Refer to the block diagram of the AD9501.
Inside the unit, there are three main subcircuits: a linear ramp
generator, an 8-bit digital-to-analog converter (DAC) and a
voltage comparator. T he rising edge of the input (T RIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
T he voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage
crosses the threshold set by the DAC output voltage. T he DAC
threshold voltage is programmed by the user with digital inputs.
Figure 1. AD9501 Internal Timing
相關PDF資料 |
PDF描述 |
|---|---|
| AD9502 | Hybrid RS-170 Video Digitizer |
| AD9502AM | Hybrid RS-170 Video Digitizer |
| AD9502BM | Hybrid RS-170 Video Digitizer |
| AD9502CM | Hybrid RS-170 Video Digitizer |
| AD9502(RS-170) | 12-Bit Dual Rail-to-Rail with I2C Interface; Package: DFN; No of Pins: 12; Temperature Range: -40°C to +85°C |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9501SE | 制造商:Analog Devices 功能描述: |
| AD9501SE/883B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9501SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9502 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
| AD9502(RS-170) | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
發布緊急采購，3分鐘左右您將得到回復。