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參數資料
| 型號： | AD9501JQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數： | 7/12頁 |
| 文件大小： | 180K |
| 代理商： | AD9501JQ |
AD9501
REV. A
–7–
Ramp charging current and DAC full-scale current are slaved
together in the AD9501 to minimize delay drift over tempera-
ture. T o preserve the unit’s low drift performance, both R
SET
and C
EX T
should have low temperature coefficients. Resistors
which are used should be 1% metal film types.
T he programmed delay (t
D
) is set by the DAC inputs, D
0
–D
7
.
Graph 1. RC Values vs. Full-Scale Delay Range (t
DFS
)
T he minimum delay through the AD9501 corresponds to an
input code of 00
H
, and FF
H
gives the full-scale delay. Any
programmed delay can be approximated by:
t
D
=
(
DAC code
/256)
×
t
DFS
T otal delay through the AD9501 for any given DAC code is
equal to:
t
TOTAL
=
t
D
+
t
PD
As shown on the block diagram, T T L/CMOS latches are
included to store the digital delay data. Data is latched when
LAT CH is HIGH. When LAT CH is LOW, the latches are
transparent, and the DAC will attempt to follow any changes on
inputs D
0
–D
7
.
T he System T iming Diagram, Figure 3, shows the timing
relationship between the input data and the latch. T he DAC
settling time (t
LD
) is approximately 30 ns. After the digital
(Programmed Delay) data is updated, a minimum 30 ns must
elapse between the time LAT CH goes high and the arrival of a
T RIGGER pulse to assure rated pulse delay accuracy.
When RESET goes HIGH, the ramp timing capacitor (C
EX T
+
8.5 pF) is discharged. T he RESET input is level-sensitive, and
overrides the T RIGGER input. T herefore, any trigger pulse
which occurs when RESET is HIGH will not produce an output
pulse. As shown on the system timing diagram, Figure 3, the
next trigger pulse should not occur before the Linear Ramp
Settling T ime (t
LRS
) interval is completed to assure rated pulse
delay accuracy.
Figure 3. AD9501 System Timing
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