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參數資料
| 型號： | AD9660KR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 200 MHz Laser Diode Driver with Light Power Control |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 256K |
| 代理商： | AD9660KR-REEL |
REV. 0
–4–
AD9660
PIN DESCRIPTIONS
Pin
Function
OUTPUT
BIAS LEVEL
Analog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally.
Analog voltage input, V
REF
to V
REF
+ 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibra-
tion as follows:
I
MONITOR
=
1.85
×
R
GAIN
+
50
TTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop
T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold
mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH.
V
BIAS LEVEL
V
REF
)
BIAS CAL
BIAS HOLD
External hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic
LOW is:
±
I
BIAS
=
18
×
10
–9
t
BIAS HOLD
C
BIAS HOLD
. Bandwidth of the loop is:
BW
=
1
2
π
(550
)C
BIASHOLD
WRITE PULSE
TTL/CMOS compatible, current control signal. Logic HIGH supplies I
MODULATION
to the laser diode. Logic
LOW turns I
MODULATION
off. Floats logic HIGH.
TTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling
calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration
mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no de-
lay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immedi-
ately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write
loop T/H and places it in hold mode. Floats logic HIGH.
Analog voltage input, V
REF
to V
REF
+1.6 V. Write current is set proportional to the input voltage during calibra-
V
WRITE LEVEL
V
REF
1.85
×
(
R
GAIN
+
50
)
WRITE CAL
WRITE LEVEL
tion as follows:
I
MONITOR
=
WRITE HOLD
External hold capacitor for the write loop T/H. Approximate droop in I
MODULATION
current while WRITE CAL is
±
I
MODULATED
=
18
×
10
9
t
WRITE HOLD
C
WRITE HOLD
logic LOW is:
. Bandwidth of the loop is:
Analog current input, I
MONITOR
, from PIN photo detector diode. SENSE IN should be connected to the cathode
of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN var-
ies slightly with temperature and current, but is typically 4.0 V.
External connection for the feedback network of the transimpedance amplifier. External feedback network, R
GAIN
and C
GAIN
, should be connected between GAIN and POWER MONITOR. See text for choosing values.
Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo
diode.
Set resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +V
S
determines offset current level. The input voltage at this node varies slightly with temperature and current, but is
typically 1.4 V. See curves. Can also be driven with a current out DAC.
TTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds I
OFFSET
to I
OUT
. Logic LOW
turns off I
OFFSET
. Floats logic HIGH.
TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables
the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V
REF
(minimizes the
output current when the device is re-enabled). DISABLE floats logic HIGH.
Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset.
Positive Power Supply. Nominally +5 V, pin connections should be tied together externally.
Ground Reference. All grounds should be tied together externally.
BW
=
1
2
π
(550
)
C
BIAS HOLD
SENSE IN
GAIN
POWER
MONITOR
OFFSET
CURRENT SET
OFFSET
PULSE
DISABLE
V
REF
+V
S
GROUND
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