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參數(shù)資料
| 型號： | AD9660KR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 200 MHz Laser Diode Driver with Light Power Control |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 256K |
| 代理商： | AD9660KR-REEL |
REV. 0
–8–
AD9660
Initial calibration
is required after power-up or any other time
the laser has been disabled. Disabling the AD9660 drives the
hold capacitors back down to V
REF
. In this case, or in any case
where the output current is more than 10% out of calibration, R
will range from 300
to 550
for the model above; the higher
value should be used for calculating the worst case calibration
time. Following the example above, if C
HOLD
were chosen as
4.5 nF, then
τ
= RC = 550
×
4.5 nF would be 2.5
μ
s. For an
initial calibration error <1%, the initial calibration time should
be >5
τ
= 12.4
μ
s.
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T/H decreases as the hold voltage approaches its
final value.
Recalibration
is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (<10%), the
resistance for the model above will be in the range of 75
to
140
. Again, the higher value should be used to estimate the
worst case time needed for recalibration.
Continuing with the example above, since the error during hold
time was chosen as 5%, we meet the criteria for recalibration
and
τ
= RC = 140
×
4.5 nF = 0.63
μ
s. To get a final error of
1% after recalibration, the 5% droop must be corrected to
within a 20% error (20%
×
5% = 1%). A 2
τ
recalibration time
of 1.26
μ
s is sufficient.
Continuous Recalibration
In applications where the hold capacitor is small (<500 pF) and
the WRITE PULSE signals always have a pulse width >25 ns,
the user may continuously calibrate the write loop. In such an
application, the WRITE CAL signal should be held logic
HIGH, and the WRITE PULSE signal will control write loop
calibration via the internal AND gate.
The bias loop may be continuously recalibrated whenever
WRITE PULSE is logic LOW.
Using this model, the voltage at the hold capacitor is
V
C
HOLD
=
V
t
=
0
+
(V
t
= ∞
V
t
=
0
) 1
e
t
τ
where t
0
is when the calibration begins (WRITE CAL or BIAS
CAL goes logic HIGH), V
t = 0
is the voltage on the hold cap at
t = 0, V
t =
∞
is the steady state voltage at the hold cap with the
loop closed, and
τ
= R
CHOLD
is the time constant. With this
model the error in V
CHOLD
for a finite calibration time, as com-
pared to V
t =
∞
, can be estimated from the following table and
chart:
Table II.
t
CALIBRATION
% Final Value
Error %
7
τ
6
τ
5
τ
4
τ
3
τ
2
τ
τ
99.9
99.7
99.2
98.1
95.0
86.5
63.2
0.09
0.25
0.79
1.83
4.97
13.5
36.8
CALIBRATION TIME – Time Constants =
t
100
30
0
0
5
1
%
2
4
20
10
3
40
50
60
70
80
90
Figure 8. Calibration Time Curve
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