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參數資料
型號: AD9803
廠商: Analog Devices, Inc.
英文描述: CCD And Video Signal Processor For Electronic Cameras(電子照相機的CCD信號和視頻信號處理器)
中文描述: CCD及視頻信號處理器電子相機(電子照相機的防治荒漠化公約信號和視頻信號處理器)
文件頁數: 3/11頁
文件大小: 105K
代理商: AD9803
–3–
REV. PrA
AD9803
DT
CCD-MODE
SPECIFICATIONS
Parameter
Min
Typ
Max
Units
POWER CONSUMPTION
190
mW
MAXIMUM CLOCK RATE
21
MHz
CDS
Gain
Allowable CCD Reset Transient
1
Max Input Range Before Saturation
1
0
500
dB
mV
mV p-p
1000
PGA
Max Input Range
Max Output Range
Digital Gain Control
Gain Control Resolution
Gain (Selected Through Serial I/F)
Gain(0) Gain(100)
Gain(1023) Gain(820)
Analog Gain Control
PGACONT1 = 0.3 V, PGACONT2 = 1.5 V
PGACONT1 = 2.4 V, PGACONT2 = 1.5 V
PGACONT1 Gain Slope
PGACONT2 Gain Slope
1000
1000
mV p-p
mV p-p
10 (Fixed)
Bits
0
30
dB
dB
0
30
14.3
0.89
dB
dB
dB/V
dB/V
BLACK-LEVEL CLAMP
Clamp Level (Selected by the Serial I/F)
CLP(0) (E-Reg 00)
CLP(1) (E-Reg 01)
CLP(2) (E-Reg 10)
CLP(3) (E-Reg 11)
32
48
64
16
LSB
LSB
LSB
LSB
TIMING SPECIFICATIONS
3
Pipeline Delay
Even-Odd Offset Correction Disabled
Even-Odd Offset Correction Enabled
Internal Clock Delay
4
(t
ID
)
Inhibited Clock Period (t
INIHIBIT
)
Output Delay (t
OD
)
Output Hold Time (t
HOLD
)
ADCCLK, SHP, SHD, Clock Period
ADCCLK Hi-Level, Or Low-Level
SHP, SHD Minimum Pulsewidth
5
SHP Rising Edge to SHD Rising Edge
5
7
Cycles
Cycles
ns
ns
ns
ns
ns
ns
ns
ns
3
15
20
2
47
20
10
20
NOTES
1
Input Range is defined as the peak-to-peak difference between the CCD's reference and data levels
3
20 pF loading; timing shown in Figure 1.
4
Internal aperture delay for actual sampling edge.
Specifications subject to change without notice.
相關PDF資料
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