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參數資料
| 型號： | AD9803 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD And Video Signal Processor For Electronic Cameras(電子照相機的CCD信號和視頻信號處理器) |
| 中文描述： | CCD及視頻信號處理器電子相機（電子照相機的防治荒漠化公約信號和視頻信號處理器） |
| 文件頁數： | 5/11頁 |
| 文件大小： | 105K |
| 代理商： | AD9803 |
AD9803
–5–
REV. PrA
OPTICAL BLACK
DT
TIMING SPECIFICATIONS
N
N+1
N+2
N+3
N+4
t
INHIBIT
t
ID
t
ID
t
OD
t
HOLD
ADCCLK RISING EDGE PLACEMENT
N–7
N–6
N–5
N–4
N–3
N–2
CCD
SHP
SHD
ADCCLK
D0–D9
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISINGEDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (
t
).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY (7 CYCLES) SHOWN WITH EVEN-ODD OFFSET CORRECTION ENABLED.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1. CCD-MODE Timing
t
ID
t
OD
t
HOLD
N
N+1
N+2
N+3
N+4
N–4
N–3
N–2
N+5
VIDEO
INPUT
ADCCLK
D0–D9
N–1
N
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2. AUX-MODE and ADC-MODE Timing
CCD
SIGNAL
CLPOB
CLPDM
PBLK
EFFECTIVE
PIXELS
BLANKING
INTERVAL
DUMMY BLACK
EFFECTIVE
PIXELS
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1
s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPOB AND CLPDM OVERWRITE PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
Figure 3. CCD-MODE Clamp Timing
Figure 4. AUX-MODE Clamp Timing
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| AD9807JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9803JST | 制造商:Rochester Electronics LLC 功能描述: |
| AD9803JST-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9803JSTRL-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9804 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9804AJST | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MHZ NO PXGA - Tape and Reel |
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