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參數資料
| 型號： | AD9806KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 10-Bit 18 MSPS CCD Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數： | 10/12頁 |
| 文件大小： | 134K |
| 代理商： | AD9806KST |
REV. 0
AD9806
–10–
REGISTER DESCRIPTION
(a)
A-REGISTER: Modes of Operation
(Power-On Default
Value = 11)
a1
a0
Modes
0
0
1
1
0
1
0
1
ADC-MODE
AUX-MODE
AUXMID-MODE
CCD-MODE
(b) B-REGISTER: Output Modes
(Default = 00)
b1
b0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
Normal
0
1
High Impedance
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
(c) C-REGISTER: Clock Modes
(Default = 00)
c1
c0
SHP-SHD Clock Pulses
Clamp Active Pulses
0
0
1
1
0
1
0
1
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
(d) D-REGISTER: Power-Down Modes
(Default = 00)
Modes
d1
d0 Description
Normal
High Speed
Power-Down1
0
0
1
0
1
0
Normal Operation
High-Speed AUX/ADC-MODE
Reference Stand-By (Same
Mode as STBY Pin 18)
Total Shut-Down
Power-Down2
1
1
(e) E-REGISTER: Clamp Level Selection
(Default = 00)
e1
e0
Clamp Level
CLP (0)
CLP (1)
CLP (2)
CLP (3)
0
0
1
1
0
1
0
1
32 LSBs
48 LSBs
64 LSBs
16 LSBs
(f) F-REGISTER:
CCD-Mode PGA
(Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2 f1 f0
CCD–Gain
Gain (0)
Gain (1023)
0 0
1 1
0 0 0 0
1 1 1 1
0 0 0
1 1 1
0
1
Minimum
Maximum
f) F-REGISTER:
AUXMID-Mode PGA
(Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 AUXMID–Gain
Gain (512)
Gain (1023) 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0
–4 dB
+14 dB
Only the 9 LSBs of F-REG are used to adjust gain.
(f) F-REGISTER:
AUX-Mode PGA
(Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2
AUX-Gain
Gain (128)
Gain (255)
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Minimum
Maximum
(g) G-REGISTER: DAC1 Input
(Default = 00 . . . 0)
g7 g6 g5 g4 g3 g2 g1 g0
DAC1 Output
Code (0)
Code (255) 1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
(h) H-REGISTER: DAC2 Input
(Default = 00 . . . 0)
h7 h6 h5 h4 h3 h2 h1 h0
DAC2 Output
Code (0)
Code (255) 1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
(j) J-REGISTER:
Even-Odd Offset Correction
(Default = 0)
j0
Even-Odd Offset Correction
0
1
Offset Correction In Use
Offset Correction Not Used
(m) M-REGISTER: DAC1 and DAC2 PDN
m0
Power-Down of 8-Bit DACs
(Default = 0)
0
1
8-Bit DACs Powered Down
8-Bit DACs Operational
NOTE
:
With the exception of a write to the PGA register dur-
ing AUX-mode, all data writes must be 10 bits. During an
AUX-mode write to the PGA register, only 8 bits of data are
required. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 9). All reads must be 10 bits to receive valid register
contents. All registers default to 0s on power-up, except for the
A-register which defaults to 11. Thus, on power-up, the AD9806
defaults to CCD mode with the 8-bit DACs powered down. Dur-
ing the power-up phase, it is recommended that SL be HIGH
and SCK be LOW to prevent accidental register write operations.
SDATA may be unknown. The RNW bit (“Read/Not Write”)
must be LOW for all write operations to the serial interface, and
HIGH when reading back from the serial interface registers.
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