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參數資料
型號: AD9806KST
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: Complete 10-Bit 18 MSPS CCD Signal Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數: 4/12頁
文件大小: 134K
代理商: AD9806KST
REV. 0
–4–
AD9806–SPECIFICATIONS
AUX-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
Normal (D-Reg 00)
High-Speed (D-Reg 01)
50
95
mW
mW
MAXIMUM CLOCK RATE
Normal (D-Reg 00)
High-Speed (D-Reg 01)
18
28.6
MHz
MHz
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Range
Min Gain (Code 128)
Max Gain (Code 255)
700
1000
mV p-p
mV p-p
Bits
7
–2
15
dB
dB
ACTIVE CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
CLP1 (E-Reg 01)
CLP2 (E-Reg 10)
CLP3 (E-Reg 11)
TIMING SPECIFICATIONS
1
Pipeline Delay
Internal Clock Delay (t
ID
)
Output Delay (t
OD
)
Output Hold Time (t
HOLD
)
32
48
64
16
LSB
LSB
LSB
LSB
9
Cycles
14.5
16
ns
ns
7
NOTES
1
20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
AUXMID-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
50
mW
MAXIMUM CLOCK RATE
18
MHz
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Range (See Figure 5b for Gain Curve)
Min Gain (Code 512)
Max Gain (Code 1023)
700
1000
mV p-p
mV p-p
Bits
9
–4
14
dB
dB
MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN)
TIMING SPECIFICATIONS
1
Pipeline Delay
Internal Clock Delay (t
ID
)
Output Delay (t
OD
)
Output Hold Time (t
HOLD
)
462
512
562
LSB
9
Cycles
14.5
16
ns
ns
7
NOTES
1
20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
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