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參數資料
| 型號： | AD9807JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數： | 11/24頁 |
| 文件大小： | 240K |
| 代理商： | AD9807JS |
AD9807/AD9805
–11–
REV. 0
7
6
5
4
3
2
1
0
8X FULL SCALE
4X FULL SCALE
2X FULL SCALE
10-BIT GAIN, 10-BIT OFFSET
11-BIT GAIN, 9-BIT OFFSET
12-BIT GAIN, 8-BIT OFFSET
COLOR0
COLOR1
Figure 5. AD9807 Configuration Register Format
Configuration Register/AD9805
T he Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 6 shows the AD9805 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a Bit
makes the corresponding condition true. Resetting Bits 0–2
disables and bypasses the digital multiplier. Bits 3–5 control
the gain and offset pin distribution. Resetting Bits 3–5 disables
and bypasses the digital subtracter and sets the gain word width
to 10. Setting any bit makes the corresponding condition true.
If Bit 3 is set, the 2 LSBs of the gain word become the 2 MSBs
of the offset word. If Bit 4 is set, the LSB of the gain word
becomes MSB of the offset word. Bits 6 and 7 direct register
data written to the MPU<7:0> bus to the appropriate red,
green or blue register.
7
6
5
4
3
2
1
0
8X FULL SCALE
4X FULL SCALE
2X FULL SCALE
8-BIT GAIN, 10-BIT OFFSET
9-BIT GAIN, 9-BIT OFFSET
10-BIT GAIN, 8-BIT OFFSET
COLOR0
COLOR1
Figure 6. AD9805 Configuration Register Format
RE GIST E R OVE RVIE W
MPU Port Map
T able II shows the MPU Port Map. T he MPU Port Map is
accessed through pins A0, A1 and A2 of the AD9807/AD9805,
and provides the decoding scheme for the various registers of
the AD9807/AD9805. When writing or reading from any of the
registers, the appropriate bits must be applied to A0–A2.
T able II. MPU Port Map Format
A2
A1
A0
Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Configuration Register
Configuration Register 2
PGA Gain Register
Odd Offset Register
Even Offset Register
Input Offset Register
RESERVED
Bayer Mode
Configuration Register/AD9807
T he Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 5 shows the AD9807 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a bit makes
the corresponding condition true. Resetting Bits 0–2 disables
and bypasses the digital multiplier. Bits 3–5 control the gain
and offset pin distribution. Resetting Bits 3–5 disables and
bypasses the digital subtracter and sets the gain word width to
12. Setting any bit makes the corresponding condition true. For
example, if Bit 3 is set, the 2 LSBs of the gain word become the
2 MSBs of the offset word. If Bit 4 is set, the LSB of the gain
word becomes MSB of the offset word. Bits 6 and 7 direct
register data written to the MPU<7:0> bus to the appropriate
red, green or blue register.
Figure 4. Block Diagram
12-BIT/10-BIT
A/D
PGA
PGA
PGA
GREEN
RED
BLUE
CDS
MUX
BANDGAP
REFERENCE
CONFIGURATION
REGISTER
2
8-10
MPU
PORT
CSB
RDB
WRB
A2
A1
A0
VREF
OFFSET<M:0>
GAIN<N:0>
CDSCLK1
CDSCLK2
VINR
VING
VINB
DOUT<11:0>/MPU<7:0>
CDS
CDS
STRTLN ADCCLK
CONFIGURATION
REGISTER
R
EVEN
G
EVEN
B
EVEN
R
G
B
R
ODD
G
ODD
B
ODD
R
G
B
INPUT OFFSET
REGISTER
12
SUBTRACTOR
DIGITAL
–
MULTIPLIER
DIGITAL
X
12
12-10/10-8
8
12
12
I/O
OEB
AD9807/AD9805
3
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