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參數資料
| 型號： | AD9814 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LABELS,CABLE MARKERS,CABLE MARKERS,LABELS, CABLE MARKERS,WIRE IDENTIFICATION AND MARKING SYSTEMS,SHRINK TUBING LABELS ,KROY RoHS Compliant: NA |
| 中文描述： | 完整的14位防治荒漠化公約/ CIS信號處理器 |
| 文件頁數： | 3/15頁 |
| 文件大小： | 160K |
| 代理商： | AD9814 |
REV. 0
–3–
AD9814
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
V
IH
V
IL
I
IH
I
IL
C
IN
2.6
V
V
μ
A
μ
A
pF
0.8
10
10
10
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
V
OH
V
OL
I
OH
I
OL
4.5
V
V
μ
A
μ
A
0.1
50
50
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
t
PRA
t
PRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2ADR
t
C2ADF
t
C2C1
t
ADC1
t
AD
300
140
45
20
40
0
10
10
50
50
0
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
t
OD
t
DV
t
HZ
6
16
5
3 (Fixed)
ns
ns
ns
Cycles
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DRVDD = +5 V, CDS Mode, f
ADCCLK
= 6 MHz, f
CDSCLK1
= f
CDSCLK2
= 2 MHz,
C
L
= 10 pF, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = +5 V, DRVDD = +5 V)
NOTES
1
The Integral Nonlinearity in measured using the “fixed endpoint” method, NOT using a “best-fit” calculation. See Definitions of Specifications.
2
The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
3
Linear input signal range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9814’s input clamp. A larger reset transient can be tolerated
by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.
RESE1V TYP
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
4
The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device.
Signals beyond the input limits will turn on the overvoltage protection diodes.
5
The PGA Gain is approximately “linear in dB” and follows the equation:
Gain
=
+
[
.
. [
4 8
]
]
5 8
1
63
– G
63
where
G
is the register value. See Figure 13.
Specifications subject to change without notice.
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