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參數(shù)資料
| 型號： | AD9816-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor |
| 中文描述： | 完整的12位6 MSPS的防治荒漠化公約/ CIS信號處理器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 171K |
| 代理商： | AD9816-EB |
–3–
REV. A
AD9816
DIGITAL SPECIFICATIONS
(T
MIN
to T
MAX
with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, f
ADCCLK
= 6 MHz,
f
CDSCLK1
= 2 MHz, f
CDSCLK2
= 2 MHz, C
L
= 10 pF unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
V
IH
V
IL
I
IH
I
IL
C
IN
3.5
V
V
μ
A
μ
A
pF
1.0
10
10
10
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
V
OH
V
OL
I
OH
I
OL
4.5
V
V
μ
A
μ
A
0.1
50
50
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(T
MIN
to T
MAX
with DVDD = +5.0 V, DRVDD = +5.0 V)
Parameter
Symbol
Min
Typ
Max
Units
CLOCK PARAMETERS
3-Channel Conversion Rate
1-Channel Conversion Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
t
CRA
t
CRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2AD
t
C2C1
t
AD
500
160
80
20
60
5
0
30
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 t
ADCLK
– 30
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
t
OD
t
DV
t
HZ
13
15
5
3 (Fixed)
ns
ns
ns
ADCCLK Cycles
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