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參數(shù)資料
| 型號： | AD9823BRUZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Correlated Double Sampler (CDS) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO14 |
| 封裝： | LEAD FREE, MO-153AB-1, TSSOP-14 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 401K |
| 代理商： | AD9823BRUZ |
AD9823
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 8
0
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD9823
TOP VIEW
(Not to Scale)
NC
NC = NO CONNECT
CLP
VDD
SHP
SHD
REFOUT
GND
CCDIN
DATAOUT
GND
NC
BYP1
BYP3
BYP2
Figure 2. Pin Configurations
Table 6. Pin Function Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
CLP
NC
VDD
REFOUT
DATAOUT
GND
BYP1
BYP2
BYP3
NC
CCDIN
GND
SHD
SHP
Type
1
DI
NC
P
AO
AO
P
AO
AO
AO
NC
AI
P
DI
DI
Description
Input Clamp Clock Input (active low, not latched internally).
No connection should be connected to GND or VDD.
Analog Supply.
Output Reference Level.
Output Data Signal.
Analog Ground.
Internal Bias Level Decoupling.
Internal Bias Level Decoupling.
Internal Bias Level Decoupling.
No connection should be connected to GND or VDD.
CCD Input.
Analog Ground.
CDS Sampling Clock Input (For CCD Data Level).
CDS Sampling Clock Input (For CCD Ref Level).
1
AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power, NC = No Connect.
SHP AND SHD TIMING
0
N
N+1
N+2
N+9
N+10
t
ID
SHP
SHD
DATACLK
(FOR AD9821)
DATAOUT
CCD
SIGNAL
t
ID
t
SHD
t
SHP
t
S1
t
S2
t
CP
t
REC
Figure 3. SHP and SHD Timing
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| AD9823KRUZ | 功能描述:IC CDS FOR DGTL CAMERA 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
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| AD9824 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit 30 MSPS CCD Signal Processor |
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