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參數資料
型號: AD9831AST
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理外設
英文描述: CMOS Complete DDS
中文描述: 16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝: TQFP-48
文件頁數: 2/16頁
文件大小: 172K
代理商: AD9831AST
REV. A
–2–
AD9831–SPECIFICATIONS
1
Parameter
SIGNAL DAC SPECIFICAT IONS
Resolution
Update Rate (f
MAX
)
I
OUT
Full Scale
AD9831A
Units
T est Conditions/Comments
10
25
4
5
1.5
Bits
MSPS nom
mA
nom
mA max
V max
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICAT IONS
2
Dynamic Specifications
Signal to Noise Ratio
T otal Harmonic Distortion
Spurious Free Dynamic Range (SFDR)
3
Narrow Band (
±
50 kHz)
±
1
±
0.5
LSB typ
LSB typ
50
–53
dB min
dBc max
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
5 V Power Supply
3 V Power Supply
–72
–70
–50
–60
1
Yes
dBc min
dBc min
dBc min
dBc typ
ms typ
Wide Band (
±
2 MHz)
Clock Feedthrough
Wake-Up T ime
4
Powerdown Option
VOLT AGE REFERENCE
Internal Reference @ +25
°
C
T
MIN
to T
MAX
REFIN Input Impedance
Reference T C
REFOUT Output Impedance
LOGIC INPUT S
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
I
AA
I
DD
I
AA
+ I
DD5
1.21
1.21
±
7%
10
100
300
Volts typ
Volts min/max
M
typ
ppm/
°
C typ
typ
V
DD
– 0.9
0.9
10
10
V
min
V
max
μ
A
max
pF
max
2.97/5.5
2.97/5.5
12
2.5 + 0.33/MHz
15
24
1
V
min/V
max
V
min/V
max
mA
max
mA typ
mA
max
mA
max
mA max
5 V Power Supply
5 V Power Supply
3 V Power Supply
5 V Power Supply
1 M
Resistor T ied Between REFOUT and AGND
Low Power Sleep Mode
6
NOT ES
1
Operating temperature range is as follows: A Version: –40
°
C to +85
°
C.
2
100% production tested.
3
f
= 6.25 MHz, Frequency Word = 5671C71C HEX , f
= 2.11 MHz.
4
See Figure 11. T o reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
6
T he Low Power Sleep Mode current is typically 2 mA when a 1 M
resistor is not tied between REFOUT and AGND.
T he AD9831 is tested with a capacitive load of 50 pF. T he part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
(V
DD
= +3.3 V
6
10%; +5 V
6
10%; AGND = DGND = 0 V; T
A
= T
MN
to T
MAX
; REFIN=
REFOUT; R
SET
= 3.9 k
V
; R
LOAD
= 300
V
for IOUT unless otherwse noted)
IOUT
COMP
REFIN
FS
REFOUT
12
AD9831
ON-BOARD
10-BIT DAC
SIN
FCONTROL
300
50pF
R
SET
3.9k
10nF
10nF
AVDD
Figure 1. Test Circuit with Which Specifications Are Tested
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PDF描述
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參數描述
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AD9832 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Complete DDS
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