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參數資料
| 型號： | AD9842A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 20 MSPS CCD Signal Processors |
| 中文描述： | 完成20 MSPS的CCD信號處理器 |
| 文件頁數： | 11/23頁 |
| 文件大?。?/td> | 272K |
| 代理商： | AD9842A |
REV. 0
AD9841A/AD9842A
–11–
PIXEL GAIN AMPLIFIER (
PxGA
) TIMING
FRAME n
VD
HD
FRAME n+1
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m
–
1
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m
–
1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
3ns MIN
GAIN0
VD
3ns MIN
GAIN1
GAIN0
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
GAIN3
GAIN2
GAINX
GAINX
5 PIXEL MIN
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
EVEN FIELD
ODD FIELD
0101...
2323...
0101...
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
0101...
2323...
0101...
HD
LINE 0
LINE 1
LINE 2
LINE m
LINE m
–
1
LINE 0
LINE 1
LINE 2
LINE m
LINE m
–
1
VD
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
3ns MIN
GAIN0
3ns MIN
GAIN1
GAIN0
GAIN3
GAIN2
GAINX
GAINX
5 PIXEL MIN
VD
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
相關PDF資料 |
PDF描述 |
|---|---|
| AD9841A | Complete 20 MSPS CCD Signal Processors |
| AD9841AJST | Trimmers; Series:T73; Resistance Tolerance: 10%; Power Rating:0.5W; Operating Temperature Range:-55 C to ? C; Resistor Element Material:Cermet; Voltage Rating:158.1V; Temperature Coefficient:100 ppm RoHS Compliant: Yes |
| AD9842AJST | Complete 20 MSPS CCD Signal Processors |
| AD9843A | Complete 10-Bit 20 MSPS CCD Signal Processor |
| AD9843AJST | Complete 10-Bit 20 MSPS CCD Signal Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9842AJST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3.3V 48LQFP - Trays 制造商:Rochester Electronics LLC 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
| AD9842AJSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3.3V 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
| AD9842AJSTZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9842-EB | 制造商:Analog Devices 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Bulk |
| AD9843A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 20 MSPS CCD Signal Processor |
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