- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373969 > AD9844AJST (ANALOG DEVICES INC) Complete 12-Bit 20 MSPS CCD Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9844AJST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Complete 12-Bit 20 MSPS CCD Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 169K |
| 代理商： | AD9844AJST |
AD9844A
–13–
REV. 0
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded
black reference pixels. Unlike some AFE architectures, the
AD9844A removes this offset in the input stage to minimize the
effect of a gain change on the system black level, usually called
the “gain step.” Another advantage of removing this offset at the
input stage is to maximize system headroom. Some area CCDs
have large black level offset voltages, which, if not corrected at
the input stage, can significantly reduce the available headroom
in the internal circuitry when higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with the typical 4 dB gain from the CDS
stage, the
total gain range for the AD9844A is 6 dB to 40 dB. A gain of
6 dB will match a 1 V input signal with the ADC full-scale range of
2 V. When compared to 1 V full-scale systems (such as ADI’s
AD9803), the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “l(fā)inear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “l(fā)inear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code Range
Gain Equation (dB)
0–511
Gain
= 20 log
10
([658 +
code
]/[658 –
code
]) – 0.35
512–1023
Gain
= (0.0354)(
code
) – 0.35
Using these two equations, the actual gain of the AD9844A can
be accurately predicted to within
±
0.5 dB. As shown in the
CCD-Mode Specifications, only the VGA gain range from 2 dB
to 36 dB is specified. This corresponds to a VGA gain code range
of 91 to 1023. The Gain Accuracy specifications also include a
CDS
gain of 4 dB, for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
V
–
127
255
383
511
639
767
895
1023
30
24
18
12
6
0
Figure 13. VGA Gain Curve (Gain from CDS Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 255 LSB may be pro-
grammed, with 8-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally, the optical
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
If external digital clamping is used during the post processing, the
AD9844A’s optical black clamping may be disabled using bit D5
in the Operation Register (see Serial Interface Timing and
Internal Register Description section). When the loop is dis-
abled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
Horizontal timing is shown in Figure 5. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the loop’s ability to
track low-frequency variations in the black level will be reduced.
A/D Converter
The AD9844A uses a high-performance ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown
in TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9844A’s ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range (see TPC 3).
AUX1-Mode
For applications that do not require CDS, the AD9844A can
be configured to sample ac-coupled waveforms. Figure 14
shows the circuit configuration for using the AUX1 channel
input (Pin 36). A single 0.1
μ
F ac-coupling capacitor is needed
between the input signal driver and the AUX1IN pin. An on-
chip dc-bias circuit sets the average value of the input signal
to approximately 0.4 V, which is referenced to the midscale code of
the ADC. The VGA Gain register provides a gain range of 0 dB
to 36 dB in this mode of operation (see VGA Gain Curve, Figure
12). The VGA gains up the signal level with respect to the 0.4V
bias level. Signal levels above the bias level will be further in-
creased to a higher ADC code, while signal levels below the bias
level will be further decreased to a lower ADC code.
AUX2-Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 15 shows the circuit
configuration for using the AUX2 channel input (Pin 34). An
external 0.1
μ
F blocking capacitor is used with the on-chip
video clamp circuit, to level-shift the input signal to a desired
reference level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the input
signal to be equal to the value programmed into the Clamp Level
register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VIII.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9845B | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845BJST | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845 | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845A | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845AJST | Complete 12-Bit 30 MSPS CCD Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9844AJSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 12-BIT 3.3V 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
| AD9844AJSTZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:12 BIT 20 MHz ANALOG FRONT END |
| AD9844-EB | 制造商:Analog Devices 功能描述: |
| AD9845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 30 MSPS CCD Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。