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參數(shù)資料
| 型號： | AD9852 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Complete-DDS Synthesizer |
| 中文描述： | 300MHz的CMOS完整的DDS合成器 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 32K |
| 代理商： | AD9852 |
3
AD9852 PRODUCT CONCEPT
____________________________________________________________________________________________
AD9852 GOAL ELECTRICAL SPECIFICATIONS
(Vs=+3 V
±
5 %, Rset=3.9 k
)
Parameter
Temp
Test Level
AD9852
Min Typ Max
Units
POWER SUPPLY
+Vs Current @:
50 MHz External Clock (PLL enabled)
P
DISS@:
50 MHz External Clock
P
DISS
Power-down Mode
+25°C
I
166
mA
+25°C
+25°C
I
I
500
10
mW
mW
NOTES
1
Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability
of the circuit may be impaired. Functional operability
under any of these conditions is not necessarily implied.
Exposure of absolute maximum rating conditions for
extended periods of time may affect device reliability.
2
The reference clock input is configured to accept a sine
wave input or a TTL-level pulse input.
3
Reference clock frequency is selected to insure second
harmonic is out of the bandwidth of interest.
4
Reference clock input=50 MHz; output frequency=40MHz;
external filter=5-pole low-pass.
EXPLANATION OF TEST LEVELS
Test Level
I - 100% Production Tested.
III - Sample Tested Only.
IV - Parameter is guaranteed by design and
characterization testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
military temperature devices; guaranteed by design
and characterization testing for industrial devices.
Table I. AD9852 PIN-FUNCTION DESCRIPTIONS
CLKIN
Rset
AGND
VDD
AVCC
W_CLK
FQ_UD
D0-D7
RESET
IOUT
IOUTB
DACBL
VINP
VINN
QOUTB
QOUT
FSELECT Frequency select input. Controls which frequency register, F0 or F1, is added to the phase accumulator
PSELECT Phase select input. Controls which phase register, P0 or P1, is added to the phase accumulator
A0-A2 Address bits. These address bits are used to select the destination register for freq/phase/control input
data
Reference clock input. This may be a sine input or continuous TTL/CMOS-level pulse train.
This is the DAC's external Rset connection. This resistor value sets the DAC fullscale output current.
Analog Ground. These pins are the ground return for the analog circuitry (DAC and comparator).
Supply voltage pins for digital circuitry.
Supply voltage for the analog circuitry (DAC and comparator).
Word load clock. This clock is used to load each of the (up to) five iterations of the 8-bit
Frequency Update. When this pin is set high, the DDS will update to the frequency
8-bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit
Reset. This is the master reset pin; when set high it clears all registers and the DAC
The true output of the differential DAC.
The complementary output of the differential DAC.
DAC Baseline. This is the DAC baseline reference; it should normally be left as a no connect.
Voltage input positive. This is the comparator's positive input pin.
Voltage input negative. This is the comparator's negative input pin.
Output complement. This is the comparator's complementary output pin.
Ouput true. This is the comparator's positive output pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852/PCB | 制造商:Analog Devices 功能描述:NCO, CMOS 300MSPS COMPLETE-DDS |
| AD9852/PCBZ | 功能描述:BOARD EVAL FOR AD9852 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD9852_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852ASQ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9852ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP |
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