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參數資料
| 型號： | AD9858PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的直接數字頻率合成器 |
| 文件頁數： | 21/32頁 |
| 文件大小： | 1412K |
| 代理商： | AD9858PCB |
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AD9858
Frequency Planning
To achieve the best possible spurious performance when using
the AD9858 in a hybrid synthesizer configuration, frequency
planning can be employed. Frequency planning consists of
being aware of the mechanisms that determine the location of
the worst-case spurs and then using the appropriate loop tuning
parameters to place these spurs either outside the loop
bandwidth, such that they are attenuated, or completely outside
the frequency range of interest.
Rev. A | Page 21 of 32
When using the fractional divider configuration, the worst-case
spurs occur whenever the images of the DAC harmonics fold
back such that they are close to the DAC fundamental or carrier
frequency. If these images fall within the loop bandwidth, they
will be gained up by approximately 20 × log
N
, where
N
is the
gain in the loop. If
N
is relatively high, these spurs can still
realize significant gain even if they are slightly outside the loop
bandwidth, since the loop attenuation rate is typically
20 dB/decade in this region. DAC images occur at
N
×
F
CLOCK
±
M
×
F
OUT
where
N
and
M
are integer multiples of
F
CLOCK
and
F
OUT
,
respectively.
Figure 20 shows a high spurious condition where the low-order
odd harmonics are folding back around the fundamental.
Figure 21 shows that the worst spurs are confined to a narrow
region around the carrier and that wideband spurs are
attenuated. Figure 17 shows an alternate frequency plan that
results in the same carrier frequency. Recall that the output
frequency of the DAC is set by the equation
(
F
OUT
=
F
CLOCK
×
FTW
/2
N
)
This makes it possible to produce the same
F
OUT
by different
combinations of
F
CLOCK
and
FTW
. In this case, the worst DAC
spurs are placed well outside the loop bandwidth such that they
are attenuated below the noise floor. Figure 24 shows a
wideband plot for this frequency plan.
Other frequency combinations that can result in high spurious
signals are when subharmonics of
F
CLOCK
fall within or near the
loop bandwidth. To avoid this, ensure that the DAC
F
OUT
is
sufficiently offset from the subharmonics of
F
CLOCK
such that
these products are attenuated by the loop.
Frequency planning for the translation loop is similar in that
the DAC images and the
F
CLOCK
subharmonics need to be
considered. Figure 25 and Figure 26 show results for a high
spurious configuration where odd order images are folding back
close to the carrier. Figure 22 and Figure 23 show an alternative
frequency plan that generates the same carrier frequency with
low spurious content. Because this loop also requires a mixer
LO frequency, additional care is required in planning for this
frequency arrangement. Generally there is some mixer LO
feedthrough. The amount of feedthrough depends on the PCB
board layout isolation as well as the mixer LO power level, but
levels of –80 dBc can typically be achieved. Figure 26 shows
results for a situation where the mixer LO component shows up
in the spectrum at 1.41 GHz, and another spur component
shows up at
Mixer LO
+
F
CLOCK
/8. This places the mixer LO
frequency well outside the bandwidth of interest, resulting in
the spectrum shown in Figure 25.
PROGRAMMING THE AD9858
The transfer of data from the user to the DDS core of the device
is a 2-step process. In a write operation, the user first writes the
data to the I/O buffer using either the parallel port (which
includes bits for address and data) or serial mode (where the
address and data are combined in a serial word). Regardless of
the method used to enter data to the I/O buffer, the DDS core
cannot access the data until the data is latched into the memory
registers from the I/O buffer. Toggling the FUD pin or changing
one of the profile select pins causes an update of all elements of
the I/O buffer memory into the DDS core’s register memory.
I/O Port Functionality
The I/O port can be operated in either serial or parallel
programming mode. Mode selection is accomplished via the
S/P Select pin. Logic 0 on this pin configures the I/O port for
serial programming, while Logic 1 configures the I/O port for
parallel programming.
The ability to read back the contents of a register is provided in
both modes to facilitate the debug process during the user’s
prototyping phase of a design. In either mode, however, the
reading back of profile registers requires that the profile select
pins (P0, P1) be configured to select the desired register bank.
When reading a register that resides in one of the profiles, the
register address acts as an offset to select one of the registers
among the group of registers defined by the profile. The profile
select pins control the base address of the register bank and
select the appropriate register grouping.
Parallel Programming Mode
In parallel programming mode, the I/O port makes use of eight
bidirectional data pins (D7 to D0), six address input pins (ADDR5
to ADDR0), a read input pin (RD), and a write input pin (WR). A
register is selected by providing the proper address combination as
defined in the register map. Read or write functionality is invoked
by pulsing the appropriate pin (RD or WR); the two operations are
mutually exclusive. The read or write data is transported on the D7
to D0 pins. The correlation between the D7 to D0 data bits and
their functionality at a specific register address is detailed in the
register map and register bit description.
Parallel I/O operation allows write access to each byte of any
register in the I/O buffer memory in a single I/O operation at a 100
MHz rate. However, unlike write operation, readback capability is
not
guaranteed at the 100 MHz rate. It is intended as a low speed
function for debug purposes. Timing for both write and read cycles
is depicted in Figure 35 and Figure 36.
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|---|---|
| AD9858 | 1 GSPS Direct Digital Synthesizer |
| AD9858FDPCB | 1 GSPS Direct Digital Synthesizer |
| AD9859 | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV-REEL7 | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
| AD9859 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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