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參數資料
| 型號： | AD9860BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, LQFP-128 |
| 文件頁數： | 17/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9860BST |
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REV. 0
AD9860/AD9862
–17–
Blank Registers
Blank registers, i.e., the registers with 0 settings and no indicated
function, are placeholders used throughout the register map for
spacing the AD9860/AD9862 control bits in a logic fashion and,
potentially can be used for future development. A low should
always be written to these registers if a write needs to take place.
SERIAL PORT INTERFACE
The Serial Port Interface (SPI) is used to write to and read from
the AD9860/AD9862 internal programmable registers. The serial
interface uses four pins: SEN, SCLK, SDIO, and SDO by default.
SEN is a serial port enable pin, SCLK is the serial clock pin,
SDIO is a bidirectional data line and SDO is a serial output pin.
SEN is an active low control gating read and write cycles. When
SEN is high, SDO and SDIO are three-stated.
SCLK is used to synchronize SPI read and writes at a maximum
bit rate of 16 MHz. Input data is registered on the rising edge and
output data transitions on the falling edge. During write opera-
tions, the registers are updated after the 16th rising clock edge
(and 24th rising clock edge for the dual byte case). Incomplete
write operations are ignored.
SDIO is an input only by default. Optionally, a 3-pin interface may
be configured using the SDIO for both input and output opera-
tions and three-stating the SDO pin (see SDIO BiDir register).
SDO is a serial output pin used for read back operations in 4-wire mode
and is three-stated when SDIO is configured for bidirectional operation.
Instruction Header
Each SPI read or write consists of an instruction header and
data. The instruction header is made up of an 8-bit word and is
used to set up the register data transfer. The 8-bit word consists
of a read/not write bit, R/nW (the MSB), followed by a double/
not single bit (2/n1) and the 6-bit register address.
Write Operations
The SPI write operation uses the instruction header to configure
a one or two register write using the 2/n1 bit. The instruction
byte followed by the register data, is written serially into the
device through the SDIO pin on rising edges of the interface
clock at SCLK. The data can be transferred MSB first or LSB first
depending on the setting of the LSB First register.
Figure 1 includes a few examples of writing data into the device.
Figure 1a shows a write using 1 Byte and MSB First mode set;
Figure 1b shows an MSB first, 2 Byte write; and Figure 1c
shows an LSB first, 2 Byte write. Note the differences between
LSB and MSB First modes: instruction header and data are
reversed, and in 2 Byte writes, the first data byte is written to
the address in the header, N and the second data byte is written
to the n
–
1 address. In LSB First mode, the first data byte is still
written to the address in the instruction header, but the second
data byte is written to the N+1 address.
SDIO
SEN
SCLK
DON’T CARE
DON’T CARE
t
S
t
DS
t
DH
t
LO
t
HI
t
CLK
t
H
A0
A1
A2
A3
A4
A5
2/n1 R/nW
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
REGISTER (N+1) DATA
REGISTER (N) DATA
INSTRUCTION HEADER (REGISTER N)
DON’T CARE
DON’T CARE
SEN
SCLK
SDIO
DON’T CARE
DON’T CARE
t
S
t
DS
t
DH
t
LO
t
HI
t
CLK
t
H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
2/n1
R/nW
REGISTER (N–1) DATA
REGISTER (N) DATA
INSTRUCTION HEADER (REGISTER N)
DON’T CARE
SEN
SCLK
SDIO
DON’T CARE
DON’T CARE
DON’T CARE
R/nW
2/n1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t
S
t
DS
t
DH
t
LO
t
HI
t
CLK
t
H
REGISTER DATA
INSTRUCTION HEADER
Figure 1. SPI Write Examples a. (top) 1 Byte, MSB First Mode; b. (middle) 2 Byte, MSB First Mode;
c. (bottom) 2 Byte, LSB First Mode
相關PDF資料 |
PDF描述 |
|---|---|
| AD9860PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862 | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9864 | IF Digitizing Subsystem |
| AD9864-EB | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9860BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9860BSTZ | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9860BSTZRL | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9860-EB | 制造商:Analog Devices 功能描述: |
| AD9860-EBZ | 功能描述:BOARD EVALUATION FOR AD9860 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發套件，板 系列:- 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產品:- 已供物品:模塊 其它名稱:SER3796 |
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