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參數資料
| 型號： | AD9862 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號前端（MxFE⑩）處理器 |
| 文件頁數： | 1/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9862 |
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Tel: 781/329-4700Fax: 781/326-8703
Analog Devices, Inc., 2002AD9860/AD9862
*
Mixed-Signal Front-End (MxFE
) Processor
for Broadband Communications
*
Protected by U.S.Patent No. 5,969,657; other patents pending.
MxFE is a trademark of Analog Devices, Inc.
GENERAL DESCRIPTION
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analog-
to-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external com-
ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain
range for both channels. The output data bus can be multi-
plexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two chan-
nels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpo-
lation rates of 2 and 4 are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
Tx DATA
PGA
PGA
DAC
DAC
FILTER
LOGIC LOW
ADC
ADC
PGA
PGA
1x
1x
IOUT+A
IOUT–A
IOUT+B
IOUT–B
AUX_ADC_B2
AUX_ADC_B1
AUX_ADC_A2
AUX_ADC_A1
AUX_DAC_C
AUX_DAC_B
AUX_DAC_A
SIGDELT
VIN+A
VIN–A
VIN+B
VIN–B
-
AUX DAC
AUX DAC
AUX DAC
AUX ADC
AUX ADC
RxA DATA
RxB DATA
SPI
OSC1
OSC2
CLKOUT1
CLKOUT2
SPI REGISTERS
CLOCK
DISBLOCK
1 ,DLL
Rx PATH
TIMING
TIMING
AD9860/AD9862
FILTER
BYDIGITAL
QUMIXER
BYDIGITAL
QUMIXER
BYPASSABLE
INLFILTER
NCO
FS/4
BDECIMATION FILTER
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
相關PDF資料 |
PDF描述 |
|---|---|
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9864 | IF Digitizing Subsystem |
| AD9864-EB | IF Digitizing Subsystem |
| AD9864BCPZ | IF Digitizing Subsystem |
| AD9864BCPZRL | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9862BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 128-LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862BSTZRL | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:MIXED SIGNAL FRONT END - Bulk |
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