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參數資料
| 型號： | AD9862 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號前端（MxFE⑩）處理器 |
| 文件頁數： | 4/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9862 |
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REV. 0
–4–
AD9860/AD9862
Test
Level
AD9860/AD9862
Typ
(20 pF Load)
Temp
Min
Max
Unit
Minimum Reset Pulsewidth Low (t
RL
)
Digital Output Rise/Fall Time
DLL Output Clock
DLL Output Duty Cycle
Tx
–
/Rx
–
Interface (See Figures 11 and 12)
TxSYNC/TxIQ Setup Time (t
Tx1
, t
Tx3
)
TxSYNC/TxIQ Hold Time (t
Tx2
, t
Tx4
)
RxSYNC/RxIQ/IF to Valid Time(t
Rx1
, t
Rx3
)
RxSYNC/RxIQ/IF Hold Time (t
Rx2
, t
Rx4
)
Serial Control Bus (See Figures 1 and 2)
Maximum SCLK Frequency (f
SCLK
)
Minimum Clock Pulsewidth High (t
HI
)
Minimum Clock Pulsewidth Low (t
LOW
)
Maximum Clock Rise/Fall Time
Minimum Data/SEN Setup Time (t
S
)
Minimum SEN/Data Hold Time (t
H
)
Minimum Data/SCLK Setup Time (t
DS
)
Minimum Data Hold Time (t
DH
)
Output Data Valid/SCLK Time (t
DV
)
NA
25
o
C
25
o
C
25
o
C
NA
III
III
III
5
2.8
32
Clock
Cycles
ns
MHz
%
4
128
50
25
o
C
25
o
C
25
o
C
25
o
C
III
III
III
III
3
3
ns
ns
ns
ns
5.2
0.2
Full
Full
Full
Full
Full
Full
Full
Full
Full
III
III
III
III
III
III
III
III
III
16
MHz
ns
ns
ms
ns
ns
ns
ns
ns
30
30
1
25
0
25
0
30
AUXILARY ADC
Conversion Rate
Input Range
Resolution
25
o
C
25
o
C
25
o
C
III
III
III
1.25
3
10
MHz
V
Bits
AUXILARY DAC
Settling Time
Output Range
Resolution
25
o
C
25
o
C
25
o
C
III
III
III
8
3
8
m
s
V
Bits
ADC TIMING
Latency (All Digital Processing Blocks Disabled)
25
o
C
III
7
Cycles
DAC Timing
Latency (All Digital Processing Blocks Disabled)
Latency (2 Interpolation Enabled)
Latency (4 Interpolation Enabled)
Additional Latency (Hilbert Filter Enabled)
Additional Latency (Coarse Modulation Enabled)
Additional Latency (Fine Modulation Enabled)
Output Settling Time (TST) (to 0.1%)
25
o
C
25
o
C
25
o
C
25
o
C
25
o
C
25
o
C
25
o
C
III
III
III
III
III
III
III
3
30
72
36
5
8
35
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ns
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Test
Level
AD9860/AD9862
Typ
PARAMETERS (continued)
Temp
Min
Max
Unit
POWER SUPPLY (continued)
Rx Path (f
ADC
= 64 MSPS)
Processing Blocks Disabled
Decimation Filter Enabled
Hilbert Filter Enabled
Hilbert and Decimation Filter Enabled
25
o
C
25
o
C
25
o
C
25
o
C
III
III
III
III
9
15
16
18.5
mA
mA
mA
mA
NOTES
1
% f
DATA
refers to the input data rate of the digital block.
2
Interpolation filter stop band is defined by image suppression of 50 dB or greater.
Specifications subject to change without notice.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9864 | IF Digitizing Subsystem |
| AD9864-EB | IF Digitizing Subsystem |
| AD9864BCPZ | IF Digitizing Subsystem |
| AD9864BCPZRL | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9862BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 128-LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862BSTZRL | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:MIXED SIGNAL FRONT END - Bulk |
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