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參數資料
| 型號： | AD9862 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號前端（MxFE⑩）處理器 |
| 文件頁數： | 25/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9862 |
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REV. 0
AD9860/AD9862
–25–
t
R
1
t
R
3
t
R
2
t
R
1
f
CLKOUT1
Rx DATA TIMING No. 1
f
Rx
= CLKOUT 4
Rx DATA TIMING No. 2
f
Rx
= CLKOUT 2
Rx DATA TIMING No. 3
f
Rx
= CLKOUT
Rx DATA TIMING No. 4
f
Rx
= 2 CLKOUT
Figure 9. Rx Timing Diagram
0: B = A
1: B = A/2
00: C = B
01: C = B/2
10: C = B/4
00: E = D
01: E = 2 D
10: E = 4 D
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
CLKOUT2
INPUT Tx DATA RATE
(SINGLE CHANNEL)
TxDAC UPDATE RATE
SINGLE CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
CLKIN
A
B
D
E
ADC DIV2
DLL MULT
INTERP
00: D = C
01: D = C/2
10: D = C/4
C
CLKOUT2 DIV
Figure 10. Single Tx Timing Block Diagram, Alternative Operation
Table I. Rx Data Timing Table
Table Ia. CLKSEL Set Logic Low
ADC
Div 2
See Figure 8 for
Relative Timing
CLKSEL
Decimate
Multiplex
Timing No. 4
Rx Data = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Mux
Not Allowed
Timing No. 3
Rx Data = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLOUT1 = 1
2
CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLOUT1 = 1
2
CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLKOUT1 = 1
2
CLKIN
Low
Div
No
Div
No
Decimation
No
Decimation
Decimation
Decimation
Table Ib. CLKSEL Set Logic High
ADC
Div 2
See Figure 8 for
Relative Timing
CLKSEL
Decimate
Multiplex
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLKOUT1 = CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLKOUT1 =
CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLKOUT1 =
CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLKOUT1 = CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLOUT1 = CLKIN
Timing No. 1
No Mux
Rx Data = 1
4
CLKOUT1
CLOUT1 = CLKIN
Timing No. 2
Mux
Rx Data(MUXED) = 1
2
CLKOUT1
CLKOUT1 = CLKIN
High
Div
No
Div
No
Decimation
No
Decimation
Decimation
Decimation
相關PDF資料 |
PDF描述 |
|---|---|
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9864 | IF Digitizing Subsystem |
| AD9864-EB | IF Digitizing Subsystem |
| AD9864BCPZ | IF Digitizing Subsystem |
| AD9864BCPZRL | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9862BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9862BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 128-LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862BSTZRL | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9862-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:MIXED SIGNAL FRONT END - Bulk |
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