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參數資料
| 型號： | AD9877ABS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Mixed-Signal Front End Set-Top Box, Cable Modem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, MQFP-100 |
| 文件頁數： | 1/36頁 |
| 文件大小： | 1094K |
| 代理商： | AD9877ABS |
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Mixed-Signal Front End
Set-Top Box, Cable Modem
AD9877
FEATURES
Low cost 3.3 V CMOS MxFE for
MCNS-DOCSIS-, DVB-, DAVIC-compliant
set-top box and cable modem applications
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Selectable interpolation filter
Analog Tx output level adjust
12-bit, 33 MSPS direct IF ADC
Dual 8-bit, 16.5 MSPS sampling IQ ADCs
Two 12-bit Σ-Δ auxiliary DACs
Direct interface to AD8321/AD8325 or
AD8322/AD8327 PGA cable driver
APPLICATIONS
Cable modems
Set-top boxes
Wireless modems
Rev.
B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
www.analog.com
FUNCTIONAL BLOCK DIAGRAM
ADC
12
12
DAC
12
12
SDELTA0
SDELTA1
REFCLK
DDS
COS
SIN
INTER-
PFILTER
Tx
CONTROL FUNCTIONS
Rx
PLL
I IN
Q IN
CA
Tx
IF IN
Tx DATA
SPORT
PROFILE
RxIQ DATA
4
2
3
RxIF DATA
ADC
8
ADC
8
Σ
-
Δ
Σ
-
Δ
AD9877
0
Figure 1.
GENERAL DESCRIPTION
The AD9877 is a single-supply set-top box and cable modem
mixed-signal front end. The device contains a transmit path
interpolation filter, complete quadrature digital upconverter,
and transmit DAC. The receive path contains a 12-bit ADC and
dual 8-bit ADCs. All internally required clocks and an output
system clock are generated by the phase-locked loop (PLL) from
a single crystal or clock input.
The transmit path interpolation filter provides upsampling
factors of 12× or 16× with an output signal bandwidth as high
as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS). The transmit DAC resolution is 12 bits
and can run at sampling rates as high as 232 MSPS. Analog
output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to
preserve SNR when reduced output levels are required.
The 12-bit ADC has excellent undersampling performance,
allowing it to typically deliver better than 10 ENOBs with IF
inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate
up to 33 MHz, allowing it to process wideband signal inputs.
Two programmable Σ-Δ DACs are available and can be used to
control external components, such as variable gain amplifiers
(VGAs) or voltage-controlled tuners.
The AD9877 integrates a CA port that enables a host processor
to control the AD8321/AD8325 or AD8322/AD8327
programmable gain amplifier (PGA) cable drivers via the
MxFE SPORT.
The AD9877 is available in a 100-lead MQFP package. It offers
enhanced receive path undersampling performance and lower
cost compared to the pin-compatible AD9873. The AD9877 is
specified over the extended industrial (40°C to +85°C)
temperature range.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9877ABS-1 | 制造商:Analog Devices 功能描述: |
| AD9877ABSZ | 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9877BS | 制造商:Analog Devices 功能描述: |
| AD9877-EB | 制造商:Analog Devices 功能描述: |
| AD9878 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End for Broadband Applications |
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