
CCD Signal Processor with Vertical Driver
and
Precision Timing
Generator
AD9925
FEATURES
Rev.
A
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infringements of patents or other rights of third parties that may result from its use.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
Integrated 10-channel V-driver Register-compatible with the AD9991 and AD9995
3-field (6-phase) vertical clock support
2 additional vertical outputs for advanced CCDs
Complete on-chip timing generator
Precision Timing
core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit 36 MHz ADC
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSPBGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
Digital video camcorders
CCD camera modules
GENERAL DESCRIPTION
The AD9925 is a complete 36 MHz front end solution for digi-
tal still camera and other CCD imaging applications. Based on
the AD9995 product, the AD9925 includes the analog front end
and a fully programmable timing generator (AFETG), combined
with a 10-channel vertical driver (V-driver). A
Precision Timing
core allows adjustment of high speed clocks with approximately
600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with
3-field (6-phase) CCDs. Two additional vertical outputs can be
used with CCDs that contain advanced video readout modes.
Voltage levels of up to +15 V and 8 V are supported.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks,
sensor gate pulses, substrate clock, and substrate bias control.
The internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-
fied over an operating temperature range of 25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9925
CDS
VGA
CLAMP
12-BIT
ADC
DCLK
MSHUT
STROBE
CLI
DOUT
VREF
6dB TO 42dB
HORIZONTAL
DRIVERS
VERTICAL
TIMING
CONTROL
RG
H1 TO H4
XV1 TO XV8
8
XSG1 TO XSG6
6
REFT REFB
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL CLOCKS
VSUB
SUBCK
HD
VD
SYNC
INTERNAL
REGISTERS
CCDIN
V-DRIVER
0dB, –2dB, –4dB
CLO
SDI
SCK
SL
RSTB
0
12
SUBCK
V1, V2
V3A, V3B
V4, V6
V5A, V5B
V7, V8
10
4
Figure 1.