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參數資料
| 型號： | AD9944KCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數： | 10/20頁 |
| 文件大小： | 485K |
| 代理商： | AD9944KCPRL |
AD9943/AD9944
TERMINOLOGY
Rev. B | Page 10 of 20
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore
every code must have a finite width. No missing codes
guaranteed to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full-signal chain specification, refers to the
peak deviation of the output of the AD9943/AD9944 from a
true straight line. The point used as zero scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
(
codes
Scale
Full
ADC
2
LSB
1
=
)
N
where
N
is the bit resolution of the ADC. For example, 1 LSB of
the AD9943 is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9943/AD9944’s power supply. The PSR specification is
calculated from the change in the data outputs for a given
step change in the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
AD9943/AD9944 until the actual sample of the input signal is
held. Both SHP and SHD sample the input signal during the
transition from low to high, so the internal delay is measured
from each clock’s rising edge to the instant the actual internal
sample is taken.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9944KCPZ | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZ | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9944KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9944KCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9944KCPZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9945 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 40 MHz CCD Signal Processor |
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