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參數資料
| 型號： | AD9949AKCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Circular Connector; No. of Contacts:61; Series:MS27474; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:24-61 RoHS Compliant: No |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數： | 31/36頁 |
| 文件大小： | 707K |
| 代理商： | AD9949AKCPZRL |
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AD9949
DRIVING THE CLI INPUT
The AD9949’s master clock input (CLI) may be used in two
different configurations, depending on the application.
Figure 41 shows a typical dc-coupled input from the master
clock source. When the dc-coupled technique is used, the
master clock signal should be at standard 3 V CMOS logic
levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor
may be used between the clock source and the CLI input. In this
configuration, the CLI input is self-biased to the proper dc volt-
age level of approximately 1.4 V. When the ac-coupled tech-
nique is used, the master clock signal can be as low as ±500 mV
in amplitude.
Rev. B | Page 31 of 36
CCD IMAGER
SIGNAL
OUT
H2
RG
H3
H4
H1
H2
H1
RG
AD9949
CCDIN
0
18
19
14
15
21
27
Figure 39. CCD Connections (2 H-Clock)
0
CCD IMAGER
SIGNAL
OUT
H4
RG
H1
H2
H3
H4
H2
H1
H3
RG
AD9949
CCDIN
14
15
18
19
21
27
Figure 40. CCD Connections (4 H-Clock)
0
CLI
AD9949
25
ASIC
MASTER CLOCK
Figure 41. CLI Connection, DC-Coupled
LPF
1nF
0
CLI
AD9949
25
ASIC
MASTER CLOCK
Figure 42. CLI Connection, AC-Coupled
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 43 shows an example CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9949 horizontal signals for this CCD, three
sequences can be used. Figure 44 shows the first sequence that
should be used during vertical blanking. During this time, there
are no valid OB pixels from the sensor, so the CLPOB signal is
not used. PBLK may be enabled during this time, because no
valid data is available.
Figure 45 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9949.
Figure 46 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
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| AD9951 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
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| AD9951YSV | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9952YSV-REEL7 | Hook-Up Wire; Conductor Size AWG:12; No. Strands x Strand Size:65 x 30; Jacket Color:Red; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1015, CSA Type TEW, JQA-F-, Passes VW-1 Flame Test; Conductor Material:Copper RoHS Compliant: Yes |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9949BCBZRL | 制造商:Analog Devices 功能描述: |
| AD9949KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 40-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT 36 MSPS, 3 V ANALOG FRONT END - Bulk |
| AD9949KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 40-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 36 MSPS, 3 V ANALOG FRONT END - Tape and Reel |
| AD9949KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9949KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
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