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參數(shù)資料
| 型號： | AD9951PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的14位，1.8伏的CMOS直接數(shù)字頻率合成 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大小： | 825K |
| 代理商： | AD9951PCB |
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AD9951
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is
high, the AD9951 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and
clock input circuitry is NOT powered down.
Rev. 0 | Page 23 of 28
When the CFR1<3> bit is high, and the PWRDWNCTL input
pin is high, the AD9951 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)
and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or powered up mode.
Table 8 indicates the logic level for each power-down bit that
drives out of the AD9951 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
For the best performance, the following layout guidelines
should be observed. Always provide the analog power supply
(AVDD) and the digital power supply (DVDD) on separate
supplies, even if just from two different voltage regulators
driven by a common supply. Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (i.e., separate the ground planes on a local-
ized board, even if the grounds connect to a common point in
the system). Bypass capacitors should be placed as close to the
device pin as possible. Usually, a multitiered bypassing scheme
consisting of a small high frequency capacitor (100 pF) placed
close to the supply pin and progressively larger capacitors (0.1 μF,
10 μF) further away from the actual supply source works best.
Table 8. Power-Down Control Functions
Control
PWRDWNCTL = 0 CFR1<3> Don’t Care
Mode Active
Software Control
Description
Digital Power-Down = CFR1<7>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
Digital Power-Down = 1’b1
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
Digital Power-Down = 1’b1
DAC Power-Down = 1’b1
Input Clock Power-Down = 1’b1
PWRDWNCTL = 1 CFR1<3> = 0
External Control,
Fast Recovery Power-Down Mode
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Full Power-Down Mode
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| AD9952YSV-REEL7 | Hook-Up Wire; Conductor Size AWG:12; No. Strands x Strand Size:65 x 30; Jacket Color:Red; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1015, CSA Type TEW, JQA-F-, Passes VW-1 Flame Test; Conductor Material:Copper RoHS Compliant: Yes |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9951YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 14-BIT DAC DDS |
| AD9951YSV-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9951YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9951YSVZ-REEL7 | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48TQFP EP TAPE AND REEL - Tape and Reel |
| AD9952 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
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