- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9952 (Analog Devices, Inc.) 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數資料
| 型號： | AD9952 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的14位，1.8伏的CMOS直接數字頻率合成 |
| 文件頁數： | 21/28頁 |
| 文件大小： | 731K |
| 代理商： | AD9952 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD9952
Rev. 0 | Page 21 of 28
SYNC_CLK
SYSCLK
A
B
DATA 2
DATA 3
DATA 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
DATA 1
DATA 2
DATA 3
I/O UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
0
Figure 22. I/O Synchronization Timing Diagram
Synchronizing Multiple AD9952s
The AD9952 product allows easy synchronization of multiple
AD9952s. There are three modes of synchronization available
to the user: an automatic synchronization mode, a software
controlled manual synchronization mode, and a hardware
controlled manual synchronization mode. In all cases, when a
user wants to synchronize two or more devices, the following
considerations must be observed. First, all units must share a
common clock source. Trace lengths and path impedance of the
clock tree must be designed to keep the phase delay of the dif-
ferent clock branches as closely matched as possible. Second, the
I/O UPDATE signal’s rising edge must be provided synchro-
nously to all devices in the system. Finally, regardless of the
internal synchronization method used, the DVDD_I/O supply
should be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master; the other device(s) will be slaved to this master. When
configured in this mode, the slaves will automatically synchro-
nize their internal clocks to the SYNC_CLK output signal of the
master device. To enter automatic synchronization mode, set the
slave device’s automatic synchronization bit (CFR1<23> = 1).
Connect the SYNC_IN input(s) to the master SYNC_CLK
output. The slave device will continuously update the phase
relationship of its SYNC_CLK until it is in phase with the
SYNC_IN input, which is the SYNC_CLK of the master device.
When attempting to synchronize devices running at SYSCLK
speeds beyond 250 MSPS, the high speed sync enhancement
enable bit should be set (CFR2<11> = 1).
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK
cycle (1/4 SYNC_CLK period). To activate the manual synchro-
nization mode, set the slave device’s software manual synchroni-
zation bit (CFR1<22> = 1). The bit (CFR1<22>) will be cleared
immediately. To advance the rising edge of the SYNC_CLK multi-
ple times, this bit will need to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN
input pin is configured such that it will now advance the rising
edge of the SYNC_CLK signal each time the device detects a
rising edge on the SYNC_IN pin. To put the device into hard-
ware manual synchronization mode, set the hardware manual
synchronization bit (CFR2<10> = 1). Unlike the software man-
ual synchronization bit, this bit does not self-clear. Once the
hardware manual synchronization mode is enabled, all rising
edges detected on the SYNC_IN input will cause the device to
advance the rising edge of the SYNC_CLK by one SYSCLK
cycle until this enable bit is cleared (CFR2<10> = 0).
Using a Single Crystal to Drive Multiple AD9952 Clock
Inputs
The AD9952 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9952s. In order to drive multiple AD9952s with one crystal,
the CRYSTAL OUT pin of the AD9952 using the external crystal
should be connected to the REFCLK input of the other AD9952.
The CRYSTAL OUT pin is static until the CFR2<9> bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
With the AD9952, the instruction byte specifies read/write
operation and the register address. Serial operations on the
AD9952 occur only at the register level, not the byte level. For
the AD9952, the serial port controller recognizes the instruction
byte register address and automatically generates the proper
register byte address. In addition, the controller expects that all
bytes of that register will be accessed. It is required that all bytes
of a register be accessed during serial I/O operations,
with one exception. The IOSYNC function can be used to
abort an I/O operation, thereby allowing some, but not all bytes
to be accessed.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9952YSV | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9953 | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953ASV | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953PCB | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9954 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9952/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Synthesizer 制造商:Analog Devices 功能描述:400 MSPS 14BIT CMOS DIRECT DGTL SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9952YSV | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48 |
| AD9952YSV-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9952YSVZ | 功能描述:IC DDS 14BIT DAC 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9952YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48 |
發布緊急采購，3分鐘左右您將得到回復。