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參數(shù)資料
| 型號： | ADAU1401YSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 785K |
| 代理商： | ADAU1401YSTZ |
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ADAU1401
I
2
C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1401 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1401 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in Figure 24.
Note that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1401 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1 (read).
This causes the ADAU1401 SDA to reverse and begin driving
Rev. 0 | Page 24 of 52
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1401.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1401 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1401 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
Chip address,
R/W = 0
AS
Subaddress high
AS
Subaddress low
AS
Data Byte 1
AS
Data Byte 2
…
AS
Data Byte N
P
Figure 22. Single-Word I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
Data-
Word 1,
Byte 1
AS
Data-
Word 1,
Byte 2
AS
Data-
Word 2,
Byte 1
AS
Data-
Word 2,
Byte 2
AS
…
P
Figure 23. Burst Mode I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
AM
Data
Byte 2
…
AM
Data
Byte N
P
Figure 24. Single-Word I
2
C Read Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data-
Word 1,
Byte 1
AM
Data-
Word 1,
Byte 2
AM
…
P
Figure 25. Burst Mode I
2
C Read Format
相關(guān)PDF資料 |
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| ADAU1401YSTZ-RL | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1401YSTZ-RL | 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1421YSTZ | 制造商:Analog Devices 功能描述: |
| ADAU1421YSTZ-REEL | 制造商:Analog Devices 功能描述: |
| ADAU1442 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Digital Audio Processor |
| ADAU1442YSVZ-3A | 功能描述:IC SIGMADSP 28B 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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