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參數資料
| 型號： | ADAU1702JSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 24/52頁 |
| 文件大小： | 773K |
| 代理商： | ADAU1702JSTZ |
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ADAU1702
I
2
C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1702 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1702 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in Figure 24.
Note that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1702 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1 (read).
This causes the ADAU1702 SDA to reverse and begin driving
Rev. 0 | Page 24 of 52
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1702.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1702 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths ranging from one to
five bytes. The ADAU1702 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
Chip address,
R/W = 0
AS
Subaddress high
AS
Subaddress low
AS
Data Byte 1
AS
Data Byte 2
…
AS
Data Byte N
P
Figure 22. Single-Word I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
Data-
Word 1,
Byte 1
AS
Data-
Word 1,
Byte 2
AS
Data-
Word 2,
Byte 1
AS
Data-
Word 2,
Byte 2
AS
…
P
Figure 23. Burst Mode I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
AM
Data
Byte 2
…
AM
Data
Byte N
P
Figure 24. Single-Word I
2
C Read Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data-
Word 1,
Byte 1
AM
Data-
Word 1,
Byte 2
AM
…
P
Figure 25. Burst Mode I
2
C Read Format
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