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參數資料
| 型號： | ADCMP580_05 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Ultrafast SiGe Voltage Comparators |
| 中文描述： | 超高速電壓比較器硅鍺 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 284K |
| 代理商： | ADCMP580_05 |
ADCMP580/ADCMP581/ADCMP582
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in the figure.
Rev. 0 | Page 5 of 16
50%
50%
V
N
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
N
V
OD
t
S
t
PL
0
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
t
PDH
Input to Output High Delay
Description
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal
low-to-high transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal
low-to-high transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the
input signal must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input
signal change.
Minimum time before the negative transition of the latch enable signal that an
input signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured
at the 20% and 80% points.
Amount of time required to transition from a high to a low output as measured
at the 20% and 80% points.
Difference between the input voltages V
P
and V
N
for output true.
Difference between the input voltages V
P
and V
N
for output false.
t
PDL
Input to Output Low Delay
t
PLOH
Latch Enable to Output High Delay
t
PLOL
Latch Enable to Output Low Delay
t
H
Minimum Hold Time
t
PL
Minimum Latch Enable Pulse Width
t
S
Minimum Setup Time
t
R
Output Rise Time
t
F
Output Fall Time
V
N
V
OD
Normal Input Voltage
Voltage Overdrive
相關PDF資料 |
PDF描述 |
|---|---|
| ADCMP580BCP-R2 | Ultrafast SiGe Voltage Comparators |
| ADCMP580BCP-RL7 | Ultrafast SiGe Voltage Comparators |
| ADCMP580BCP-WP | Ultrafast SiGe Voltage Comparators |
| ADCMP581 | Ultrafast SiGe Voltage Comparators |
| ADCMP581BCP-R2 | Ultrafast SiGe Voltage Comparators |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP580BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast SiGe Voltage Comparator |
| ADCMP580BCP-R2 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R |
| ADCMP580BCP-RL7 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R |
| ADCMP580BCP-WP | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC ((NS)) |
| ADCMP580BCPZ-R2 | 功能描述:IC COMPARATOR CML UFAST 16-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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