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參數資料
| 型號： | ADCMP607 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| 中文描述： | 軌到軌，速度非常快，2.5 V至5.5 V，單電源白血病比較 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 280K |
| 代理商： | ADCMP607 |
ADCMP606/ADCMP607
TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
Rev. 0 | Page 5 of 16
1.1V
50%
V
N
± V
OS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
V
IN
V
OD
t
S
t
PL
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
0
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
t
F
Output fall time
Description
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
Difference between the input voltages V
A
and V
B
.
t
H
Minimum hold time
t
PDH
Input to output high delay
t
PDL
Input to output low delay
t
PL
t
PLOH
Minimum latch enable pulse width
Latch enable to output high delay
t
PLOL
Latch enable to output low delay
t
R
Output rise time
t
S
Minimum setup time
V
OD
Voltage overdrive
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| ADCMP607BCPZ-R2 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP607BCPZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP607BCPZ-R7 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP607BCPZ-WP | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數:4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP608 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP608_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
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