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參數資料
型號: ADE7753ARS
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調理
英文描述: Active and Apparent Energy Metering IC with di/dt sensor interface
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: MO-150AE, SSOP-20
文件頁數: 24/38頁
文件大小: 449K
代理商: ADE7753ARS
ADE7753
–24–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Reactive
Power
Active
Power
Apparent
Power
θ
Figure 42 - Power triangle
( )
ω
t
(
)
θ
ω
+
=
=
t
i
t
t
v
sin
I
2
)
(
sin
V
2
)
(
rms
rms
(19)
)
2
cos(
)
cos(
)
(
)
(
)
(
)
(
θ
ω
θ
+
=
×
I
=
t
I
V
V
t
p
t
i
t
v
t
p
rms
rms
rms
rms
(20)
T he Apparent Power (AP) is defined as V
rms
x I
rms
. T his
expression is independent from the phase angle between the
current and the voltage.
Figure 43 illustrates graphically the signal processing in each
phase for the calculation of the Apparent Power in the
AD E 7753.
Current RMS Signal - i(t)
Voltage RMS Signal - v(t)
MULTIPLIER
Apparent Power
Signal - P
Irms
Vrms
00h
00h
AD055h
VAGAIN
1C82B3h
17D338h
Figure 43 - Apparent Power Signal Processing
T he gain of the Apparent Energy can be adjusted by using the
multiplier and VA Gain register (VAGAIN[11:0]). T he gain
is adjusted by writing a 2’s complement, 12-bit word to the
VAGAIN register. Below is the expression that shows how
the gain adjustment is related to the contents of the VA Gain
register.
=
Power
Apparent
VAGAIN
Output
+
1
×
12
2
VAGAIN
For example when 7FFh is written to the VA Gain register
the Power output is scaled up by 50%. 7FFh = 2047d,
2047/2
12
= 0.5. Similarly, 800h = -2047 Dec (signed 2’s
Complement) and power output is scaled by –50%.
T he Apparent Power is calculated with the C urrent and
Voltage RMS values obtained in the RMS blocks of the
AD E 7753. Shown in F igure 44 is the maximum code
(Hexadecimal) output range of the Apparent Power signal.
Note that the output range changes depending on the contents
of the Apparent Power Gain registers. T he minimum output
range is given when the Apparent Power Gain register
content is equal to 800h and the maximum range is given by
writing 7FFh to the Apparent Power Gain register. T his can
be used to calibrate the Apparent Power (or Energy) calcu-
lation in the ADE7753 -see
Apparent Power calculation
.
00000h
AD055h
5682Bh
103880h
VAGAIN[11:0]
Apparent Power
Calibration Range
000h
7FFh
800h
Apparent Power 100% FS
Apparent Power 150% FS
Apparent Power 50% FS
Voltage and Current channel inputs: 0.5V / GAIN
Figure 44- Apparent Power Calculation Output range
Apparent Power Offset Calibration
Each RMS measurement includes an offset compensation
register to calibrate and eliminate the DC component in the
RMS value -see
Channel 1 RMS calculation and Channel 2 RMS
calculation
. T he channel 1 and channel 2 RMS values are then
multiplied together in the Apparent Power signal processing.
As no additional offsets are created in the multiplication of
the RMS values, there is no specific offset compensation in
the Apparent Power signal processing. T he offset compensa-
tion of the Apparent Power measurement is done by calibrating
each individual RMS measurements.
APPARE NT E NE RGY CALCULAT ION
T he Apparent Energy is given as the integral of the Apparent
Power.
T he AD E7753 achieves the integration of the Apparent
Power signal by continuously accumulating the Apparent
Power signal in an internal 48-bit register. T he Apparent
Energy register (VAENERGY [23:0]) represents the upper
24 bits of this internal register. T his discrete time accumu-
lation or summation is equivalent to integration in continuous
time. Equation 23 below expresses the relationship
=
=
0
n
dt
t
Power
Apparent
Energy
Apparent
=
)
(
(21)
×
0
)
(
T
T
nT
Power
Apparent
Lim
Energy
Apparent
(22)
Where n is the discrete time sample number and T is the
sample period.
T he discrete time sample period (T ) for the accumulation
register in the ADE7753 is 1.1μs (4/CLK IN).
Figure 44 shows a graphical representation of this discrete
time integration or accumulation. T he Apparent Power
signal is continuously added to the internal register. T his
addition is a signed addition even if the Apparent Energy
remains theoretically always positive.
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