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參數資料
| 型號： | ADF4107BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | 16-9 (4 Contacts) Pin Insert; For Use With:Amphenol MIL-C-5015 97 Series Circular Connectors; No. of Contacts:4 |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7000 MHz, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, LFCSP-20 |
| 文件頁數： | 10/20頁 |
| 文件大小： | 792K |
| 代理商： | ADF4107BCP |
ADF4107
Phase Frequency Detector and Charge
Pump
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 20 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. See Figure 23.
HI
HI
D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
V
P
CHARGE
PUMP
Figure 20. PFD Simplified Schematic and Timing (in Lock)
MUXOUT and Lock Detect
The output multiplexer on the ADF4107 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 25 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, this output will be high with
narrow, low-going pulses.
DGND
DV
DD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
Figure 21. MUXOUT Circuit
Input Shift Register
The ADF4107 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Figure 22 shows a summary of
how the latches are programmed.
Table 5. C2, C1 Truth Table
Control Bits
C2
C1
0
0
0
1
1
0
1
1
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Rev. 0 | Page 10 of 20
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| ADF4107BCPZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 7GHZ, LFCSP- |
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