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參數資料
| 型號： | ADF4107BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | 16-9 (4 Contacts) Pin Insert; For Use With:Amphenol MIL-C-5015 97 Series Circular Connectors; No. of Contacts:4 |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7000 MHz, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, LFCSP-20 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 792K |
| 代理商： | ADF4107BCP |
ADF4107
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Rev. 0 | Page 6 of 20
R
SET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
V
P
DV
DD
ADF4107
TOP VIEW
(Not to Scale)
TSSOP
Figure 3. ADF4107 TSSOP (Top View)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
RF
IN
B
RF
IN
A
2
A
D
A
D
R
I
D
D
4
5
1
1
1
1
R
S
V
P
D
D
D
D
PIN 1
ADF4107
TOP VIEW
CSP
(Chip Scale Package)
Figure 4. ADF4107 Chip Scale Package
Table 4. Pin Functional Descriptions
Mnemonic
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage
potential at the
R
SET
pin is 0.66 V. The relationship between
I
CP
and
R
SET
is
5
25
=
R
SET
SET
R
MAX
CP
I
so, with
R
SET
= 5.1 k,
I
CP MAX
= 5 mA.
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,
typically 100 pF. See Figure 18.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of 100 k. See
Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking
the pin high will power up the device, depending on the status of the power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift
register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance
CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the
latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This voltage should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can be set to 5
V and used to drive a VCO with a tuning range of up to 5 V.
CP
CPGND
AGND
RF
IN
B
RF
IN
A
AV
DD
REF
IN
DGND
CE
CLK
DATA
LE
MUXOUT
DV
DD
V
P
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