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參數(shù)資料
| 型號： | ADF4117BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 226K |
| 代理商： | ADF4117BRU |
ADF4116/ADF4117/ADF4118
–
18
–
REV. 0
APPLICATIONS SECTION
Local Oscillator for GSM Base Station Transmitter
Figure 26 shows the ADF4117/ADF4118 being used with a
VCO to produce the LO for a GSM base station transmitter.
The reference input signal is applied to the circuit at FREF
IN
and, in this case, is terminated in 50
. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50
termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4117/ADF1118.
The charge pump output of the ADF4117/ADF1118 (Pin 2)
drives the loop filter. In calculating the loop filter component
values, a number of items need to be considered. In this example,
the loop filter was designed so that the overall phase margin for
the system would be 45 degrees. Other PLL system specifica-
tions are given below:
K
D
= 1 mA
K
V
= 12 MHz/V
Loop Bandwidth = 20 kHz
F
REF
= 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 27.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50
matching between the VCO output, the RF output and
the RF
IN
terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 26, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
VCO190-902T
V
CC
18
100pF
100pF
18
18
RF
OUT
V
DD
V
P
AV
DD
DV
DD
ADF4117/
ADF4118
V
P
CP
0.15nF
620pF
3.3k
7
15
16
2
14
6
5
8
FREF
IN
1000pF 1000pF
51
MUXOUT
LOCK
DETECT
51
100pF
3
4
9
100pF
C
A
D
RF
IN
A
RF
IN
B
CE
CLK
DATA
LE
S
DECOUPLING CAPACITORS (10 F/10pF) ON AV
, DV
, V
OF THE
ADF4117/ADF4118 AND ON V
OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO AID CLARITY.
FL
O
10k
1.5nF
27k
REF
IN
Figure 26. Local Oscillator for GSM Base Station
SHUTDOWN CIRCUIT
The attached circuit in Figure 27 shows how to shut down both
the ADF4116 family and the accompanying VCO. The ADG702
switch goes open circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SOIC packages.
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 28 shows the combination
available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified
±
0.02 dB and
±
0.004 dB gain and offset match-
ing characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The Local Oscillator (LO) is implemented using the ADF4117/
ADF4118. In this case, the OSC 3B1-13M0 provides the
stable 13 MHz reference frequency. The system is designed
for a 200 kHz channel spacing and an output center frequency
of 1960 MHz. The target application is a WCDMA base sta-
tion transmitter. Typical phase noise performance from this LO
is –85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is
driven in single-ended fashion. LOIN is ac-coupled to ground
with the 100 pF capacitor and LOIP is driven through the ac-
coupling capacitor from a 50
source. An LO drive level of
between –6 dBm and –12 dBm is required. The circuit of Figure
28 gives a typical level of –8 dBm.
The RF output is designed to drive a 50
load but must be
ac-coupled as shown in Figure 28. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power will
be around –10 dBm.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4117BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R |
| ADF4117BRU-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4117BRUZ | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4117BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4117BRUZ-RL | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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