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參數(shù)資料
| 型號(hào)： | ADF4206 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | 雙射頻鎖相環(huán)頻率合成器 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大小： | 206K |
| 代理商： | ADF4206 |
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADF4206/ADF4207/ADF4208
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
Dual RF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
CLOCK
DATA
LE
22-BIT
DATA
REGISTER
MUXOUT
ADF4206/ADF4207/ADF4208
CP
RF1
CP
RF2
PHASE
COMPARATOR
OUTPUT
MUX
14-BIT RF2
R-COUNTER
OSC
IN
OSC
OUT
RF1
IN
A
RF1
IN
B
V
DD
1
V
DD
2
V
P
1
V
P
2
AGND
RF1
DGND
RF1
DGND
RF2
AGND
RF2
SDOUT
RF2
PRESCALER
RF2
IN
A
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
RF2
IN
B
N = BP + A
CHARGE
PUMP
RF2
LOCK
DETECT
14-BIT RF1
R-COUNTER
RF1
PRESCALER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
N = BP + A
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4207: 1.1 GHz/1.1 GHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Selectable Charge Pump Currents
On-Chip Oscillator Circuit
Selectable Dual Modulus Prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4206 family of dual frequency synthesizers can be
used to implement local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
Each synthesizer consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, programmable A and B counters and a dual-
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
counters, in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter), allows selectable REFIN frequen-
cies at the PFD input. The on-chip oscillator circuitry allows
the reference input to be derived from crystal oscillators.
A complete PLL (Phase-Locked Loop) can be implemented if
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADF4206BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
| ADF4206BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R |
| ADF4206BRU-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R |
| ADF4206BRUZ | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
| ADF4206BRUZ-R7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R |
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