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參數(shù)資料
| 型號： | ADF4206 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | 雙射頻鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 206K |
| 代理商： | ADF4206 |
REV. 0
ADF4206/ADF4207/ADF4208
–5–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin
No.
ADF4206/
ADF4207
ADF4208
Function
Positive Power Supply for the RF1 Section. A 0.1
μ
F capacitor should be connected between
this pin and the RF1 ground pin, DGND
RF1
. V
DD
1 should have a value of between 2.7 V and
5.5 V. V
DD
1 must have the same potential as V
DD
2.
Power Supply for the RF1 Charge Pump. This should be greater than or equal to V
DD
.
Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.
Ground Pin for the RF1 Digital Circuitry.
Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to
the ground plane with a small bypass capacitor.
Ground Pin for the RF1 Analog Circuitry.
Oscillator Input. It has a V
DD
/2 threshold and can be driven from an external CMOS or TTL
logic gate.
Oscillator Output.
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled
Reference Frequency to be accessed externally. See Table V.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 22-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected using the control bits.
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground
plane with a small bypass capacitor.
Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the
external VCO.
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives
the input to an external VCO.
Power Supply for the RF2 Charge Pump. This should be greater than or equal to V
DD
.
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1
μ
F capacitor
should be connected between this pin and the RF2 ground Pin, DGND
RF2
. V
DD
2 should
have a value between 2.7 V and 5.5 V. V
DD
2 must have the same potential as V
DD
1.
1
V
DD
1
V
DD
1
2
3
V
P
1
CP
RF1
V
P
1
CP
RF1
4
5
6
DGND
RF1
RF1
IN
OSC
IN
DGND
RF1
RF1
IN
A
RF
IN
B
7
8
OSC
OUT
MUXOUT
AGND
RF1
OSC
IN
9
10
CLK
DATA
OSC
OUT
MUXOUT
11
LE
CLK
12
RF2
IN
DATA
13
DGND
RF2
LE
14
15
CP
RF2
V
P
2
AGND
RF2
RF2
IN
B
16
V
DD
2
RF2
IN
A
17
18
DGND
RF2
CP
RF2
19
20
V
P
2
V
DD
2
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
DD
1
V
P
1
CP
RF1
DGND
RF1
RF1
IN
OSC
IN
OSC
OUT
MUXOUT
V
DD
2
V
P
2
CP
RF2
DGND
RF2
RF2
IN
LE
DATA
CLK
ADF4206/
ADF4207
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ADF4208
V
DD
1
V
P
1
CP
RF1
DGND
RF1
RF1
IN
A
OSC
IN
OSC
OUT
MUXOUT
V
DD
2
V
P
2
CP
RF2
AGND
RF2
LE
DATA
CLK
RF1
IN
B
AGND
RF1
RF2
IN
B
RF2
IN
A
DGND
RF2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADF4206BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
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| ADF4206BRU-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R |
| ADF4206BRUZ | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
| ADF4206BRUZ-R7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R |
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