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參數資料
| 型號： | ADF4251BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual Fractional-N/Integer-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24 |
| 封裝： | 4 X 4 MM, MO-200-VGGD2, LFCSP-24 |
| 文件頁數： | 22/28頁 |
| 文件大小： | 387K |
| 代理商： | ADF4251BCP |
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REV. 0
–22–
ADF4251
RF Phase Detector Polarity
DB7 in the ADF4251 sets the RF phase detector polarity.
When the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
RF Charge Pump Current Setting
DB9 and DB10 set the RF charge pump current setting. This
should be set to whatever charge pump current the loop filter
has been designed with (see Table V).
RF Test Modes
These bits should be set to 0, 0, 0 for normal operation.
MASTER REGISTER
(Address R3)
With R3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be
programmed. Table VI shows the input data format for program-
ming the Master Register.
RF and IF Counter Reset
DB3 is the counter reset bit for the ADF4251. When this is 1,
both the RF and IF R, INT, and MOD counters are held in reset.
For normal operation, this bit should be 0. Upon powering up, the
DB3 bit needs to be disabled, the INT counter resumes counting
in
“
close
”
alignment with the R counter. (The maximum error is
one prescaler cycle).
Charge Pump Three-State
This bit puts both the RF and IF charge pump into three-state
mode when programmed to a 1. It should be set to 0 for normal
operation.
Power-Down
R3[3] on the ADF4251 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on both
the RF and IF sections. Setting this bit to 0 will return the RF
and IF sections to normal operation. While in software power-
down, the part will retain all information in its registers. Only
when supplies are removed will the register contents be lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The RF and IF counters are forced to their load state conditions.
3. The RF and IF charge pumps are forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RF
IN
input and IF
IN
input are debiased.
6. The oscillator input buffer circuitry is disabled.
7. The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by R3[10
–
7] on the
ADF4251. Table VI shows the truth table.
If the user updates the RF control register or the IF control
register, the MUXOUT contents will be lost. To retrieve the
MUXOUT signal, the user must write to the Master Register.
IF N DIVIDER REGISTER
(Address R4)
With R4[2, 1, 0] set to [1, 0, 0], the on-chip IF N divider register
will be programmed. Table VII shows the input data format for
programming this register.
IF CP Gain
When set to 1, this bit changes the IF charge pump current
setting to its maximum value. When the bit is set to 0, the charge
pump current reverts back to its previous state.
IF Prescaler
The dual-modulus prescaler (P/P + 1), along with the IF A and
IF B counters, determine the overall division ratio, N, to be real-
ized (N = PB + A) from the IF
IN
to the IF PFD input. Operating
at CML levels, it takes the clock from the IF input stage and divides
it down to a manageable frequency for the CMOS counters. It
is based on a synchronous 4/5 core. See Equation 2 and Table VII.
IF B and A Counter
The IF A and IF B counters, in conjunction with the dual modu-
lus prescaler, make it possible to generate output frequencies
that are spaced only by the reference frequency (REF
IN
), divided
by R. The equation for the IF
OUT
VCO frequency is given in
Equation 2.
IF R DIVIDER REGISTER
(Address R5)
With R5[2, 1, 0] set to 1, 0, 1, the on-chip IF R divider register
will be programmed. Table VIII shows the input data format for
programming this register.
IF REF
IN
Doubler
Setting this bit to 0 feeds the REF
IN
signal directly to the 15-bit
IF R counter. Setting this bit to 1 multiplies the REF
IN
frequency by a factor of 2 before feeding into the 15-bit IF R
counter.
15-Bit IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the IF phase frequency detector (PFD). Division ratios from
1 to 32767 are allowed.
IF CONTROL REGISTER
(Address R6)
With R6[2, 1, 0] set to 1, 1, 0, the on-chip IF control register
will be programmed. Table IX shows the input data format for
programming this register. Upon initialization, DB15
–
DB11
should all be set to 0.
IF Counter Reset
DB3 is the IF counter reset bit for the ADF4251. When this is
1, the IF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
IF Charge Pump Three-State
This bit puts the IF charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
IF Power-Down
DB5 on the ADF4251 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on the IF
section. Setting this bit to 0 will return the section to normal
operation. While in software power-down, the part will retain all
information in its registers. Only when supplies are removed will
the register contents be lost.
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