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參數(shù)資料
| 型號： | ADF4360-2 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 336K |
| 代理商： | ADF4360-2 |
PRELIMINARY TECHNICAL DATA
ADF4360-2
REV. PrA 07/03
–15–
N COUNTER LATCH
With (C2, C1) = (1,0), the N Counters Latch is programmed.
A Counter Latch
A5 - A1 program the 5-bit A counter. The divide range is 0 (00000)
to 31 (11111).
Reserved Bits
DB7 is a spare bit and has been designated as “Reserved”. It
should be programmed to “0”.
B Counter Latch
B13 - B1 program the B counter. The divide range here is 3
(00.....0011) to 8191 (11....111).
Overall Divide Range
The overall divide range is defined by ((PxB) + A), where P is the
prescaler value.
CP Gain Bit
DB21 of the N Counter Latch in the ADF4360 family is the Charge
Pump Gain bit. When this is programmed to a “1” then Current
Setting 2 is used. When programmed to a “0”, Current Setting 1 is
used. This bit can also be programmed via DB10 of the Control
Latch. The bit will always reflect the latest value written to it,
whether this is through the Control Latch or the N Counter Latch.
Divide by 2
DB22 is the divide-by-2 bit. When set to a “1”, the output divide
by 2 function is chosen. When it is set to “0”, normal operation
occurs.
Divide by 2 Select
DB23 is the divide-by-2 select bit. When this is programmed to a
“1”, the divide-by-2 output is selected as the prescaler input.
When it is set to a “0”, the fundamental is used as the prescaler
input. For Example: Using the Output Divide by Two feature, and a
PFD frequency of 200kHz the user will need a value of N = 10000 to
generate 1GHz. With the divide by two select bit high, the user may
keep N = 5000.
R Counter
R1 to R14 sets the counter divide ratio. The divide range is 1
(00.....001) to 16383 (111......111).
Anti-Backlash Pulse Width
DB16 and DB17 set the anti-backlash pulse width.
Lock Detect Precision Bit
DB18 is the Lock Detect Precision Bit and sets the number of
references cycles with less than 15ns phase error for entering
the locked state. With LDP at “1”, 5 cycles are taken and with
LDP at “0”, 3 cycles are taken.
Test Mode Bit.
DB19 is the Test Mode Bit (TMB) and should be set to zero.
With TMB = 0, the contents of the Test Mode Latch are
ignored and normal operation occurs as determined by the
contents of the Control Latch, R Counter Latch, and N
Counter Latch. Please note that Test Modes are for Factory
testing only, and should not be programmed by the user.
Band Select Clock Bits
These Bits set a divider for the band select logic clock input,
The output of the R Counter is by default the value used to
clock the band select logic, but if this value is too high
(>1MHz), a divider can be switched in to divide the R counter
output to a smaller value. See Table 4.
Reserved Bits
DB23 - DB22 are spare bits and have been designated as
“Reserved”. They should be programmed to “0”.
R COUNTER LATCH
With (C2, C1) = (0,1), the R Counter Latch is programmed.
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